module __float32__from_int32_internal(
  input wire sign,
  input wire [31:0] fraction,
  input wire [7:0] lz,
  output wire [31:0] out
);
  wire [7:0] add_254;
  wire [32:0] fraction__1;
  wire fraction__5;
  wire [2:0] normal_chunk;
  wire [1:0] half_way_chunk;
  wire [23:0] add_276;
  wire [6:0] sub_277;
  wire [7:0] bexp;
  wire [7:0] sub_282;
  wire [7:0] bexp__1;
  wire [22:0] fraction__4;
  wire or_289;
  wire [31:0] result__1;
  assign add_254 = lz + 8'h03;
  assign fraction__1 = add_254 >= 8'h21 ? 33'h0_0000_0000 : {1'h0, fraction} << add_254;
  assign fraction__5 = fraction__1[7] | fraction__1[6:0] != 7'h00;
  assign normal_chunk = {fraction__1[9:8], fraction__5};
  assign half_way_chunk = fraction__1[10:9];
  assign add_276 = {1'h0, fraction__1[32:10]} + {23'h00_0000, normal_chunk > 3'h4 | half_way_chunk == 2'h3};
  assign sub_277 = 7'h4e - lz[7:1];
  assign bexp = {sub_277, ~lz[0]};
  assign sub_282 = 8'h9e - lz;
  assign bexp__1 = add_276[23] ? sub_282 : bexp;
  assign fraction__4 = add_276[22:0];
  assign or_289 = bexp__1[7] | (&bexp__1[6:0]) | fraction__4 != 23'h00_0000;
  assign result__1 = {or_289 & sign, bexp__1 & {8{or_289}}, fraction__4};
  assign out = result__1;
endmodule