module __float64__ldexp(
  input wire [63:0] f,
  input wire [31:0] e,
  output wire [63:0] out
);
  wire [10:0] f_bexp__1;
  wire [10:0] literal_452;
  wire eq_454;
  wire [10:0] add_455;
  wire [51:0] tuple_index_459;
  wire [32:0] e__1;
  wire [51:0] f__1_fraction;
  wire [32:0] MAX_EXPONENT;
  wire [10:0] BIAS;
  wire [32:0] MIN_EXPONENT;
  wire sgt_471;
  wire [10:0] add_472;
  wire [10:0] literal_473;
  wire slt_476;
  wire [10:0] result__2_bexp__1;
  wire eq_482;
  wire eq_483;
  wire f_sign;
  wire nor_491;
  wire [51:0] sel_498;
  wire [63:0] result__5;
  assign f_bexp__1 = f[62:52];
  assign literal_452 = 11'h000;
  assign eq_454 = f_bexp__1 == literal_452;
  assign add_455 = f_bexp__1 + 11'h401;
  assign tuple_index_459 = f[51:0];
  assign e__1 = {{1{e[31]}}, e} + {{22{add_455[10]}}, add_455};
  assign f__1_fraction = tuple_index_459 & {52{~eq_454}};
  assign MAX_EXPONENT = 33'h0_0000_03ff;
  assign BIAS = 11'h3ff;
  assign MIN_EXPONENT = 33'h1_ffff_fc02;
  assign sgt_471 = $signed(e__1) > $signed(MAX_EXPONENT);
  assign add_472 = e__1[10:0] + BIAS;
  assign literal_473 = 11'h7ff;
  assign slt_476 = $signed(e__1) < $signed(MIN_EXPONENT);
  assign result__2_bexp__1 = slt_476 ? {10'h000, e__1 == 33'h1_ffff_fc01 & f__1_fraction == 52'hf_ffff_ffff_ffff} : (sgt_471 ? literal_473 : add_472);
  assign eq_482 = f_bexp__1 == literal_473;
  assign eq_483 = f__1_fraction == 52'h0_0000_0000_0000;
  assign f_sign = f[63:63];
  assign nor_491 = ~(~eq_482 | eq_483);
  assign sel_498 = nor_491 ? 52'h8_0000_0000_0000 : tuple_index_459 & {52{~(result__2_bexp__1 == literal_452 | slt_476 | sgt_471 | eq_454)}};
  assign result__5 = {~(nor_491 | ~f_sign), nor_491 ? literal_473 : (eq_454 | eq_482 & eq_483 ? f_bexp__1 : result__2_bexp__1), sel_498};
  assign out = result__5;
endmodule