Action `df7a73a4f3809219dad419b62fe1cd66787f041b685a34261f9b45946edaf676`

Summary

state: not queued

kind: combo_verilog_to_yosys_abc_aig

subject: verilog=a3f1e6f617bb top=__acm_random__rng_next64

crate:v0.3.0dso:-driver:-

Upstream Dependencies

Role	Action ID	State	Kind	Subject	Output
`verilog_action_id`	`a3f1e6f617bb60775dd85af552086a51699a28a3c73538d89f9a788197097373`	done	`ir_fn_to_combinational_verilog`	ir=697c5a37be06 top=__acm_random__rng_next64 system_verilog=false	`verilog_file payload/result.v`

Failure

timeout at 2026-02-20T05:06:50.262447361+00:00 by unknown-host:2098204:web-runner-25

summary: TIMEOUT(300) docker run exceeded 300 seconds (container=xlsynth-bvc-run-df7a73a4f3809219-2098204-196)

TIMEOUT(300) docker run exceeded 300 seconds (container=xlsynth-bvc-run-df7a73a4f3809219-2098204-196)
command:
docker run --name xlsynth-bvc-run-df7a73a4f3809219-2098204-196 --rm --pull never --network none -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/artifacts/a3/f1/a3f1e6f617bb60775dd85af552086a51699a28a3c73538d89f9a788197097373/payload/result.v:/inputs/input.v:ro -v /home/cdleary/proj/xlsynth-bvc/flows/yosys_to_aig.ys:/inputs/flow.ys:ro -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/.staging/df7a73a4f3809219dad419b62fe1cd66787f041b685a34261f9b45946edaf676-2098204-1771563710029553917/payload:/outputs -e READ_VERILOG_FLAGS= -e VERILOG_TOP_MODULE_NAME=__acm_random__rng_next64 xlsynth-bvc-yosys-abc:ubuntu24.04 bash -lc 
set -euo pipefail
{
  echo "read_verilog ${READ_VERILOG_FLAGS} /inputs/input.v"
  if [ -n "${VERILOG_TOP_MODULE_NAME:-}" ]; then
    echo "hierarchy -check -top ${VERILOG_TOP_MODULE_NAME}"
  fi
  echo "script /inputs/flow.ys"
  echo "write_aiger /outputs/result.aig"
} > /tmp/run.ys
yosys -s /tmp/run.ys
test -s /outputs/result.aig

cleanup: removed timed-out container
stdout:

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.33 (git sha1 2584903a060)


-- Executing script file `/tmp/run.ys' --

1. Executing Verilog-2005 frontend: /inputs/input.v
Parsing Verilog input from `/inputs/input.v' to AST representation.
Generating RTLIL representation for module `\__acm_random__rng_next64'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \__acm_random__rng_next64

2.2. Analyzing design hierarchy..
Top module:  \__acm_random__rng_next64
Removed 0 unused modules.

-- Executing script file `/inputs/flow.ys' --

3. Executing PROC pass (convert processes to netlists).

3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 8 assignments to connections.

3.4. Executing PROC_INIT pass (extract init attributes).

3.5. Executing PROC_ARST pass (detect async resets in processes).

3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\__acm_random__rng_next64.$proc$/inputs/input.v:0$16'.
Creating decoders for process `\__acm_random__rng_next64.$proc$/inputs/input.v:0$10'.

3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\__acm_random__rng_next64.\umul47b_32b_x_15b$func$/inputs/input.v:31$2.$result' from process `\__acm_random__rng_next64.$proc$/inputs/input.v:0$16'.
No latch inferred for signal `\__acm_random__rng_next64.\umul47b_32b_x_15b$func$/inputs/input.v:31$4.$result' from process `\__acm_random__rng_next64.$proc$/inputs/input.v:0$16'.
No latch inferred for signal `\__acm_random__rng_next64.\umul47b_32b_x_15b$func$/inputs/input.v:31$4.lhs' from process `\__acm_random__rng_next64.$proc$/inputs/input.v:0$16'.
No latch inferred for signal `\__acm_random__rng_next64.\umul47b_32b_x_15b$func$/inputs/input.v:31$4.rhs' from process `\__acm_random__rng_next64.$proc$/inputs/input.v:0$16'.
No latch inferred for signal `\__acm_random__rng_next64.\umul47b_32b_x_15b$func$/inputs/input.v:27$1.$result' from process `\__acm_random__rng_next64.$proc$/inputs/input.v:0$10'.
No latch inferred for signal `\__acm_random__rng_next64.\umul47b_32b_x_15b$func$/inputs/input.v:27$3.$result' from process `\__acm_random__rng_next64.$proc$/inputs/input.v:0$10'.
No latch inferred for signal `\__acm_random__rng_next64.\umul47b_32b_x_15b$func$/inputs/input.v:27$3.lhs' from process `\__acm_random__rng_next64.$proc$/inputs/input.v:0$10'.
No latch inferred for signal `\__acm_random__rng_next64.\umul47b_32b_x_15b$func$/inputs/input.v:27$3.rhs' from process `\__acm_random__rng_next64.$proc$/inputs/input.v:0$10'.

3.9. Executing PROC_DFF pass (convert process syncs to FFs).

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `__acm_random__rng_next64.$proc$/inputs/input.v:0$16'.
Removing empty process `__acm_random__rng_next64.$proc$/inputs/input.v:0$10'.
Cleaned up 0 empty switches.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module __acm_random__rng_next64.

4. Executing OPT pass (performing simple optimizations).

4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module __acm_random__rng_next64.

4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__acm_random__rng_next64'.
Removed a total of 0 cells.

4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \__acm_random__rng_next64..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \__acm_random__rng_next64.
Performed a total of 0 changes.

4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__acm_random__rng_next64'.
Removed a total of 0 cells.

4.6. Executing OPT_DFF pass (perform DFF optimizations).

4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \__acm_random__rng_next64..
Removed 0 unused cells and 19 unused wires.
<suppressed ~1 debug messages>

4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module __acm_random__rng_next64.

4.9. Rerunning OPT passes. (Maybe there is more to do..)

4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \__acm_random__rng_next64..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \__acm_random__rng_next64.
Performed a total of 0 changes.

4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__acm_random__rng_next64'.
Removed a total of 0 cells.

4.13. Executing OPT_DFF pass (perform DFF optimizations).

4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \__acm_random__rng_next64..

4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module __acm_random__rng_next64.

4.16. Finished OPT passes. (There is nothing left to do.)

5. Executing TECHMAP pass (map to technology primitives).

5.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

5.2. Continuing TECHMAP pass.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=33:B_SIGNED=0:B_WIDTH=33:Y_WIDTH=33:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=33:B_SIGNED=0:B_WIDTH=33:Y_WIDTH=33:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=33:B_SIGNED=0:B_WIDTH=33:Y_WIDTH=33:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=63:B_SIGNED=0:B_WIDTH=63:Y_WIDTH=63:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=63:B_SIGNED=0:B_WIDTH=63:Y_WIDTH=63:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=63:B_SIGNED=0:B_WIDTH=63:Y_WIDTH=63:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=63:B_SIGNED=0:B_WIDTH=63:Y_WIDTH=63:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=63:B_SIGNED=0:B_WIDTH=63:Y_WIDTH=63:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=63:B_SIGNED=0:B_WIDTH=63:Y_WIDTH=63:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=15:Y_WIDTH=47:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=15:Y_WIDTH=47:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=15:Y_WIDTH=47:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_90_alu for cells of type $alu.
Using template $paramod$cc6a978c1b57cdb49efcec348c88d8e28bf1a01f\_90_alu for cells of type $alu.
Using template $paramod$d2455104d750d99d2c2ad573b55e75e857f021ee\_90_alu for cells of type $alu.
Using extmapper maccmap for cells of type $macc.
  add \s * 15'100000110100111 (32x15 bits, unsigned)
  add \new_seed * 15'100000110100111 (32x15 bits, unsigned)
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000100000 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $not.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000100001 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000111111 for cells of type $lcu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000101111 for cells of type $fa.
Using template $paramod$86ddd617693f8aad0133a455d4259f73429c7e32\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $or.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000101111 for cells of type $lcu.
No more expansions possible.
<suppressed ~2487 debug messages>

6. Executing ABC pass (technology mapping using ABC).

6.1. Extracting gate netlist of module `\__acm_random__rng_next64' to `<abc-temp-dir>/input.blif'..
Extracted 10514 gates and 10548 wires to a netlist network with 32 inputs and 95 outputs.

6.1.1. Executing ABC.

stderr:

Attempted Command

docker run --name xlsynth-bvc-run-df7a73a4f3809219-2098204-196 --rm --pull never --network none -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/artifacts/a3/f1/a3f1e6f617bb60775dd85af552086a51699a28a3c73538d89f9a788197097373/payload/result.v:/inputs/input.v:ro -v /home/cdleary/proj/xlsynth-bvc/flows/yosys_to_aig.ys:/inputs/flow.ys:ro -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/.staging/df7a73a4f3809219dad419b62fe1cd66787f041b685a34261f9b45946edaf676-2098204-1771563710029553917/payload:/outputs -e READ_VERILOG_FLAGS= -e VERILOG_TOP_MODULE_NAME=__acm_random__rng_next64 xlsynth-bvc-yosys-abc:ubuntu24.04 bash -lc

Action JSON

{
  "action": "combo_verilog_to_yosys_abc_aig",
  "verilog_action_id": "a3f1e6f617bb60775dd85af552086a51699a28a3c73538d89f9a788197097373",
  "verilog_top_module_name": "__acm_random__rng_next64",
  "yosys_script_ref": {
    "path": "flows/yosys_to_aig.ys",
    "sha256": "b96ea6e2f96ce4442a7370366c13c8f8a38cfd4e0fcc12860d940d3f0a28b07a"
  },
  "runtime": {
    "docker_image": "xlsynth-bvc-yosys-abc:ubuntu24.04",
    "dockerfile": "docker/yosys-abc.Dockerfile"
  }
}

Action df7a73a4f3809219dad419b62fe1cd66787f041b685a34261f9b45946edaf676

Summary

Upstream Dependencies

Failure

Action JSON

Action `df7a73a4f3809219dad419b62fe1cd66787f041b685a34261f9b45946edaf676`