module __fixed_point__aligned_width(
  input wire [31:0] NB_A,
  input wire [31:0] BE_A,
  input wire [31:0] NB_B,
  input wire [31:0] BE_B,
  output wire [31:0] out
);
  wire literal_172;
  wire [32:0] add_177;
  wire [32:0] literal_178;
  wire [32:0] add_179;
  wire [32:0] msb_a;
  wire [32:0] msb_b;
  wire [31:0] msb__1;
  wire [31:0] literal_186;
  wire [31:0] sub_192;
  wire [31:0] num_bits__1;
  assign literal_172 = 1'h0;
  assign add_177 = {literal_172, NB_A} + {{1{BE_A[31]}}, BE_A};
  assign literal_178 = 33'h1_ffff_ffff;
  assign add_179 = {literal_172, NB_B} + {{1{BE_B[31]}}, BE_B};
  assign msb_a = add_177 + literal_178;
  assign msb_b = add_179 + literal_178;
  assign msb__1 = $signed(msb_a) > $signed(msb_b) ? msb_a[31:0] : msb_b[31:0];
  assign literal_186 = 32'h0000_0000;
  assign sub_192 = msb__1 - ($signed(BE_A) < $signed(BE_B) ? BE_A : BE_B);
  assign num_bits__1 = sub_192 + 32'h0000_0001;
  assign out = num_bits__1;
endmodule