module __float32__gt_2(
  input wire [31:0] x,
  input wire [31:0] y,
  output wire out
);
  function automatic priority_sel_1b_3way (input reg [2:0] sel, input reg case0, input reg case1, input reg case2, input reg default_value);
    begin
      casez (sel)
        3'b??1: begin
          priority_sel_1b_3way = case0;
        end
        3'b?10: begin
          priority_sel_1b_3way = case1;
        end
        3'b100: begin
          priority_sel_1b_3way = case2;
        end
        3'b000: begin
          priority_sel_1b_3way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_1b_3way = 1'dx;
        end
      endcase
    end
  endfunction
  wire [7:0] x_bexp__1;
  wire [7:0] literal_486;
  wire [7:0] y_bexp__2;
  wire eq_488;
  wire eq_489;
  wire [22:0] x_fraction__1;
  wire [22:0] y_fraction__1;
  wire [7:0] literal_496;
  wire [22:0] literal_497;
  wire x_sign__2;
  wire y_sign__1;
  wire [22:0] x__1_fraction__2;
  wire [22:0] y__1_fraction__2;
  wire eq_506;
  wire eq_exp;
  wire gt_fraction;
  wire and_510;
  wire and_511;
  wire and_513;
  wire gt_exp;
  wire nor_516;
  wire abs_gt;
  wire and_532;
  wire result;
  wire and_539;
  assign x_bexp__1 = x[30:23];
  assign literal_486 = 8'h00;
  assign y_bexp__2 = y[30:23];
  assign eq_488 = x_bexp__1 == literal_486;
  assign eq_489 = y_bexp__2 == literal_486;
  assign x_fraction__1 = x[22:0];
  assign y_fraction__1 = y[22:0];
  assign literal_496 = 8'hff;
  assign literal_497 = 23'h00_0000;
  assign x_sign__2 = x[31:31];
  assign y_sign__1 = y[31:31];
  assign x__1_fraction__2 = x_fraction__1 & {23{~eq_488}};
  assign y__1_fraction__2 = y_fraction__1 & {23{~eq_489}};
  assign eq_506 = x_sign__2 == y_sign__1;
  assign eq_exp = x_bexp__1 == y_bexp__2;
  assign gt_fraction = x__1_fraction__2 > y__1_fraction__2;
  assign and_510 = x_bexp__1 == literal_496 & x_fraction__1 != literal_497;
  assign and_511 = y_bexp__2 == literal_496 & y_fraction__1 != literal_497;
  assign and_513 = eq_488 & eq_489;
  assign gt_exp = x_bexp__1 > y_bexp__2;
  assign nor_516 = ~(and_510 | and_511);
  assign abs_gt = gt_exp | eq_exp & gt_fraction;
  assign and_532 = ~abs_gt & ~(nor_516 & (eq_506 & eq_exp & x__1_fraction__2 == y__1_fraction__2 | and_513));
  assign result = priority_sel_1b_3way({~(~x_sign__2 | y_sign__1), ~(x_sign__2 | ~y_sign__1), ~(x_sign__2 | y_sign__1)}, abs_gt, 1'h1, 1'h0, and_532);
  assign and_539 = ~(nor_516 & (eq_506 & eq_exp & x_fraction__1 == y_fraction__1 | and_513)) & ~(and_510 | and_511 | ~result);
  assign out = and_539;
endmodule