module __std__next_pow2(
  input wire [31:0] n,
  output wire [31:0] out
);
  wire [31:0] add_3190;
  wire [31:0] reverse_3191;
  wire [32:0] one_hot_3192;
  wire [6:0] sub_3198;
  wire [31:0] and_3202;
  wire [1:0] result_squeezed;
  wire [1:0] literal_3206;
  wire [1:0] result__1_squeezed;
  wire [3:0] result__1_squeezed__1;
  wire [3:0] literal_3211;
  wire [3:0] result__2_squeezed;
  wire [7:0] result__2_squeezed__1;
  wire [7:0] literal_3216;
  wire [7:0] result__3_squeezed;
  wire [15:0] result__3_squeezed__1;
  wire [15:0] result__4_squeezed_const_msb_bits;
  wire [15:0] result__4_squeezed;
  wire [31:0] result__4;
  wire [31:0] result__5;
  wire [31:0] result__32;
  assign add_3190 = n + 32'hffff_ffff;
  assign reverse_3191 = {add_3190[0], add_3190[1], add_3190[2], add_3190[3], add_3190[4], add_3190[5], add_3190[6], add_3190[7], add_3190[8], add_3190[9], add_3190[10], add_3190[11], add_3190[12], add_3190[13], add_3190[14], add_3190[15], add_3190[16], add_3190[17], add_3190[18], add_3190[19], add_3190[20], add_3190[21], add_3190[22], add_3190[23], add_3190[24], add_3190[25], add_3190[26], add_3190[27], add_3190[28], add_3190[29], add_3190[30], add_3190[31]};
  assign one_hot_3192 = {reverse_3191[31:0] == 32'h0000_0000, reverse_3191[31] && reverse_3191[30:0] == 31'h0000_0000, reverse_3191[30] && reverse_3191[29:0] == 30'h0000_0000, reverse_3191[29] && reverse_3191[28:0] == 29'h0000_0000, reverse_3191[28] && reverse_3191[27:0] == 28'h000_0000, reverse_3191[27] && reverse_3191[26:0] == 27'h000_0000, reverse_3191[26] && reverse_3191[25:0] == 26'h000_0000, reverse_3191[25] && reverse_3191[24:0] == 25'h000_0000, reverse_3191[24] && reverse_3191[23:0] == 24'h00_0000, reverse_3191[23] && reverse_3191[22:0] == 23'h00_0000, reverse_3191[22] && reverse_3191[21:0] == 22'h00_0000, reverse_3191[21] && reverse_3191[20:0] == 21'h00_0000, reverse_3191[20] && reverse_3191[19:0] == 20'h0_0000, reverse_3191[19] && reverse_3191[18:0] == 19'h0_0000, reverse_3191[18] && reverse_3191[17:0] == 18'h0_0000, reverse_3191[17] && reverse_3191[16:0] == 17'h0_0000, reverse_3191[16] && reverse_3191[15:0] == 16'h0000, reverse_3191[15] && reverse_3191[14:0] == 15'h0000, reverse_3191[14] && reverse_3191[13:0] == 14'h0000, reverse_3191[13] && reverse_3191[12:0] == 13'h0000, reverse_3191[12] && reverse_3191[11:0] == 12'h000, reverse_3191[11] && reverse_3191[10:0] == 11'h000, reverse_3191[10] && reverse_3191[9:0] == 10'h000, reverse_3191[9] && reverse_3191[8:0] == 9'h000, reverse_3191[8] && reverse_3191[7:0] == 8'h00, reverse_3191[7] && reverse_3191[6:0] == 7'h00, reverse_3191[6] && reverse_3191[5:0] == 6'h00, reverse_3191[5] && reverse_3191[4:0] == 5'h00, reverse_3191[4] && reverse_3191[3:0] == 4'h0, reverse_3191[3] && reverse_3191[2:0] == 3'h0, reverse_3191[2] && reverse_3191[1:0] == 2'h0, reverse_3191[1] && !reverse_3191[0], reverse_3191[0]};
  assign sub_3198 = 7'h20 - {1'h0, {one_hot_3192[32], one_hot_3192[16] | one_hot_3192[17] | one_hot_3192[18] | one_hot_3192[19] | one_hot_3192[20] | one_hot_3192[21] | one_hot_3192[22] | one_hot_3192[23] | one_hot_3192[24] | one_hot_3192[25] | one_hot_3192[26] | one_hot_3192[27] | one_hot_3192[28] | one_hot_3192[29] | one_hot_3192[30] | one_hot_3192[31], one_hot_3192[8] | one_hot_3192[9] | one_hot_3192[10] | one_hot_3192[11] | one_hot_3192[12] | one_hot_3192[13] | one_hot_3192[14] | one_hot_3192[15] | one_hot_3192[24] | one_hot_3192[25] | one_hot_3192[26] | one_hot_3192[27] | one_hot_3192[28] | one_hot_3192[29] | one_hot_3192[30] | one_hot_3192[31], one_hot_3192[4] | one_hot_3192[5] | one_hot_3192[6] | one_hot_3192[7] | one_hot_3192[12] | one_hot_3192[13] | one_hot_3192[14] | one_hot_3192[15] | one_hot_3192[20] | one_hot_3192[21] | one_hot_3192[22] | one_hot_3192[23] | one_hot_3192[28] | one_hot_3192[29] | one_hot_3192[30] | one_hot_3192[31], one_hot_3192[2] | one_hot_3192[3] | one_hot_3192[6] | one_hot_3192[7] | one_hot_3192[10] | one_hot_3192[11] | one_hot_3192[14] | one_hot_3192[15] | one_hot_3192[18] | one_hot_3192[19] | one_hot_3192[22] | one_hot_3192[23] | one_hot_3192[26] | one_hot_3192[27] | one_hot_3192[30] | one_hot_3192[31], one_hot_3192[1] | one_hot_3192[3] | one_hot_3192[5] | one_hot_3192[7] | one_hot_3192[9] | one_hot_3192[11] | one_hot_3192[13] | one_hot_3192[15] | one_hot_3192[17] | one_hot_3192[19] | one_hot_3192[21] | one_hot_3192[23] | one_hot_3192[25] | one_hot_3192[27] | one_hot_3192[29] | one_hot_3192[31]}};
  assign and_3202 = {{25{sub_3198[6]}}, sub_3198} & {32{n != 32'h0000_0000}};
  assign result_squeezed = 2'h1;
  assign literal_3206 = 2'h0;
  assign result__1_squeezed = and_3202[0] ? 2'h2 : result_squeezed;
  assign result__1_squeezed__1 = {literal_3206, result__1_squeezed};
  assign literal_3211 = 4'h0;
  assign result__2_squeezed = and_3202[1] ? {result__1_squeezed, literal_3206} : result__1_squeezed__1;
  assign result__2_squeezed__1 = {literal_3211, result__2_squeezed};
  assign literal_3216 = 8'h00;
  assign result__3_squeezed = and_3202[2] ? {result__2_squeezed, literal_3211} : result__2_squeezed__1;
  assign result__3_squeezed__1 = {literal_3216, result__3_squeezed};
  assign result__4_squeezed_const_msb_bits = 16'h0000;
  assign result__4_squeezed = and_3202[3] ? {result__3_squeezed, literal_3216} : result__3_squeezed__1;
  assign result__4 = {result__4_squeezed_const_msb_bits, result__4_squeezed};
  assign result__5 = and_3202[4] ? {result__4_squeezed, result__4_squeezed_const_msb_bits} : result__4;
  assign result__32 = result__5 & {32{~(and_3202[31] | and_3202[5])}};
  assign out = result__32;
endmodule