module __float32__add(
  input wire [31:0] x,
  input wire [31:0] y,
  output wire [31:0] out
);
  function automatic [1:0] priority_sel_2b_2way (input reg [1:0] sel, input reg [1:0] case0, input reg [1:0] case1, input reg [1:0] default_value);
    begin
      casez (sel)
        2'b?1: begin
          priority_sel_2b_2way = case0;
        end
        2'b10: begin
          priority_sel_2b_2way = case1;
        end
        2'b00: begin
          priority_sel_2b_2way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_2b_2way = 2'dx;
        end
      endcase
    end
  endfunction
  function automatic [2:0] priority_sel_3b_2way (input reg [1:0] sel, input reg [2:0] case0, input reg [2:0] case1, input reg [2:0] default_value);
    begin
      casez (sel)
        2'b?1: begin
          priority_sel_3b_2way = case0;
        end
        2'b10: begin
          priority_sel_3b_2way = case1;
        end
        2'b00: begin
          priority_sel_3b_2way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_3b_2way = 3'dx;
        end
      endcase
    end
  endfunction
  function automatic priority_sel_1b_2way (input reg [1:0] sel, input reg case0, input reg case1, input reg default_value);
    begin
      casez (sel)
        2'b?1: begin
          priority_sel_1b_2way = case0;
        end
        2'b10: begin
          priority_sel_1b_2way = case1;
        end
        2'b00: begin
          priority_sel_1b_2way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_1b_2way = 1'dx;
        end
      endcase
    end
  endfunction
  wire [7:0] y_bexp__1;
  wire [7:0] x_bexp__1;
  wire [7:0] y_bexpnot;
  wire [8:0] x_bexp_extended__1;
  wire [8:0] y_bexpnot_extended;
  wire [8:0] full_result;
  wire overflow_detected;
  wire [22:0] tuple_index_31171;
  wire [22:0] tuple_index_31172;
  wire [7:0] x_bexp;
  wire [7:0] y_bexp;
  wire [22:0] x_fraction;
  wire [22:0] y_fraction;
  wire nc;
  wire [23:0] fraction_x;
  wire [23:0] fraction_y;
  wire [23:0] sign_ext_31185;
  wire [7:0] narrowed_result;
  wire [7:0] x_bexpor_mask;
  wire tuple_index_31189;
  wire tuple_index_31190;
  wire [23:0] fraction_x__1;
  wire [23:0] fraction_y__1;
  wire [2:0] xddend_x__1_squeezed_const_lsb_bits;
  wire [7:0] result;
  wire x_sign;
  wire y_sign;
  wire [24:0] wide_x_squeezed;
  wire [26:0] wide_y_shift_bits;
  wire [7:0] shift;
  wire [26:0] shrl_31204;
  wire [27:0] shll_31206;
  wire [24:0] xddend_x__1_squeezed;
  wire [25:0] add_31217;
  wire sticky;
  wire [27:0] concat_31223;
  wire [27:0] xbs_fraction;
  wire carry_bit;
  wire nor_31264;
  wire nor_31259;
  wire nor_31260;
  wire nor_31250;
  wire nor_31251;
  wire and_31293;
  wire nor_31295;
  wire nor_31297;
  wire and_31290;
  wire nor_31286;
  wire and_31282;
  wire nor_31283;
  wire nor_31277;
  wire nor_31279;
  wire and_31322;
  wire nor_31303;
  wire nor_31304;
  wire and_31343;
  wire [1:0] priority_sel_31344;
  wire and_31339;
  wire and_31335;
  wire and_31331;
  wire [2:0] concat_31357;
  wire [2:0] concat_31354;
  wire [2:0] concat_31353;
  wire [2:0] concat_31351;
  wire [2:0] concat_31350;
  wire and_31362;
  wire [3:0] concat_31366;
  wire [3:0] sel_31475;
  wire [4:0] concat_31374;
  wire [4:0] leading_zeroes;
  wire [28:0] cancel_fraction;
  wire [26:0] cancel_fraction__1;
  wire [26:0] carry_fraction__1;
  wire [26:0] shifted_fraction;
  wire [2:0] normal_chunk;
  wire [2:0] fraction_shift__3;
  wire [1:0] half_way_chunk;
  wire do_round_up;
  wire [24:0] add_31394;
  wire rounding_carry;
  wire [8:0] add_31407;
  wire [5:0] sub_31408;
  wire fraction_is_zero;
  wire [9:0] wide_exponent_associative_element;
  wire [9:0] wide_exponent_associative_element__1;
  wire [9:0] wide_exponent;
  wire [9:0] wide_exponent__1;
  wire [7:0] MAX_EXPONENT;
  wire [8:0] wide_exponent__2;
  wire eq_31423;
  wire eq_31424;
  wire eq_31425;
  wire eq_31426;
  wire [2:0] fraction_shift__2;
  wire is_operand_inf;
  wire and_reduce_31444;
  wire has_pos_inf;
  wire has_neg_inf;
  wire [27:0] rounded_fraction;
  wire [2:0] fraction_shift__1;
  wire [27:0] shrl_31457;
  wire is_result_nan;
  wire result_sign;
  wire [22:0] result_fraction;
  wire [22:0] sign_ext_31463;
  wire result_sign__1;
  wire [22:0] result_fraction__3;
  wire [22:0] FRACTION_HIGH_BIT;
  wire result_sign__2;
  wire [7:0] result_exponent__2;
  wire [22:0] result_fraction__4;
  assign y_bexp__1 = y[30:23];
  assign x_bexp__1 = x[30:23];
  assign y_bexpnot = ~y_bexp__1;
  assign x_bexp_extended__1 = {1'h0, x_bexp__1};
  assign y_bexpnot_extended = {1'h0, y_bexpnot};
  assign full_result = x_bexp_extended__1 + y_bexpnot_extended;
  assign overflow_detected = full_result[8];
  assign tuple_index_31171 = y[22:0];
  assign tuple_index_31172 = x[22:0];
  assign x_bexp = overflow_detected ? x_bexp__1 : y_bexp__1;
  assign y_bexp = overflow_detected ? y_bexp__1 : x_bexp__1;
  assign x_fraction = overflow_detected ? tuple_index_31172 : tuple_index_31171;
  assign y_fraction = overflow_detected ? tuple_index_31171 : tuple_index_31172;
  assign nc = ~overflow_detected;
  assign fraction_x = {1'h1, x_fraction};
  assign fraction_y = {1'h1, y_fraction};
  assign sign_ext_31185 = {24{y_bexp != 8'h00}};
  assign narrowed_result = full_result[7:0];
  assign x_bexpor_mask = {8{nc}};
  assign tuple_index_31189 = y[31:31];
  assign tuple_index_31190 = x[31:31];
  assign fraction_x__1 = fraction_x & {24{x_bexp != 8'h00}};
  assign fraction_y__1 = fraction_y & sign_ext_31185;
  assign xddend_x__1_squeezed_const_lsb_bits = 3'h0;
  assign result = narrowed_result ^ x_bexpor_mask;
  assign x_sign = overflow_detected ? tuple_index_31190 : tuple_index_31189;
  assign y_sign = overflow_detected ? tuple_index_31189 : tuple_index_31190;
  assign wide_x_squeezed = {1'h0, fraction_x__1};
  assign wide_y_shift_bits = {fraction_y__1, xddend_x__1_squeezed_const_lsb_bits};
  assign shift = result + {7'h00, overflow_detected};
  assign shrl_31204 = shift >= 8'h1b ? 27'h000_0000 : wide_y_shift_bits >> shift;
  assign shll_31206 = shift >= 8'h1c ? 28'h000_0000 : 28'hfff_ffff << shift;
  assign xddend_x__1_squeezed = x_sign ^ y_sign ? -wide_x_squeezed : wide_x_squeezed;
  assign add_31217 = {{1{xddend_x__1_squeezed[24]}}, xddend_x__1_squeezed} + {2'h0, shrl_31204[26:3]};
  assign sticky = ~({1'h0, ~y_fraction} | ~sign_ext_31185 | shll_31206[26:3]) != 24'h00_0000;
  assign concat_31223 = {add_31217[24:0], shrl_31204[2:1], shrl_31204[0] | sticky};
  assign xbs_fraction = add_31217[25] ? -concat_31223 : concat_31223;
  assign carry_bit = xbs_fraction[27];
  assign nor_31264 = ~(xbs_fraction[25] | xbs_fraction[24]);
  assign nor_31259 = ~(xbs_fraction[17] | xbs_fraction[16]);
  assign nor_31260 = ~(xbs_fraction[19] | xbs_fraction[18]);
  assign nor_31250 = ~(xbs_fraction[9] | xbs_fraction[8]);
  assign nor_31251 = ~(xbs_fraction[11] | xbs_fraction[10]);
  assign and_31293 = ~(carry_bit | xbs_fraction[26]) & nor_31264;
  assign nor_31295 = ~(xbs_fraction[21] | xbs_fraction[20]);
  assign nor_31297 = ~(carry_bit | ~xbs_fraction[26]);
  assign and_31290 = nor_31260 & nor_31259;
  assign nor_31286 = ~(xbs_fraction[13] | xbs_fraction[12]);
  assign and_31282 = nor_31251 & nor_31250;
  assign nor_31283 = ~(xbs_fraction[11] | ~xbs_fraction[10]);
  assign nor_31277 = ~(xbs_fraction[5] | xbs_fraction[4]);
  assign nor_31279 = ~(xbs_fraction[7] | xbs_fraction[6]);
  assign and_31322 = ~(xbs_fraction[23] | xbs_fraction[22]) & nor_31295;
  assign nor_31303 = ~(xbs_fraction[1] | xbs_fraction[0]);
  assign nor_31304 = ~(xbs_fraction[3] | xbs_fraction[2]);
  assign and_31343 = and_31293 & and_31322;
  assign priority_sel_31344 = priority_sel_2b_2way({~(carry_bit | xbs_fraction[26] | nor_31264), and_31293}, {nor_31297, 1'h0}, {1'h1, ~(xbs_fraction[25] | ~xbs_fraction[24])}, {1'h0, nor_31297});
  assign and_31339 = ~(xbs_fraction[15] | xbs_fraction[14]) & nor_31286;
  assign and_31335 = nor_31279 & nor_31277;
  assign and_31331 = nor_31304 & nor_31303;
  assign concat_31357 = {1'h1, ~(xbs_fraction[23] | xbs_fraction[22] | nor_31295) ? {1'h1, ~(xbs_fraction[21] | ~xbs_fraction[20])} : {1'h0, ~(xbs_fraction[23] | ~xbs_fraction[22])}};
  assign concat_31354 = {and_31290, priority_sel_2b_2way({~(xbs_fraction[19] | xbs_fraction[18] | nor_31259), and_31290}, 2'h0, {1'h1, ~(xbs_fraction[17] | ~xbs_fraction[16])}, {nor_31260, ~(xbs_fraction[19] | ~xbs_fraction[18])})};
  assign concat_31353 = {1'h1, ~(xbs_fraction[15] | xbs_fraction[14] | nor_31286) ? {1'h1, ~(xbs_fraction[13] | ~xbs_fraction[12])} : {1'h0, ~(xbs_fraction[15] | ~xbs_fraction[14])}};
  assign concat_31351 = {and_31282, priority_sel_2b_2way({~(xbs_fraction[11] | xbs_fraction[10] | nor_31250), and_31282}, {nor_31283, 1'h0}, {1'h1, ~(xbs_fraction[9] | ~xbs_fraction[8])}, {nor_31251, nor_31283})};
  assign concat_31350 = {1'h1, ~(xbs_fraction[7] | xbs_fraction[6] | nor_31277) ? {1'h1, ~(xbs_fraction[5] | ~xbs_fraction[4])} : {nor_31279, ~(xbs_fraction[7] | ~xbs_fraction[6])}};
  assign and_31362 = and_31290 & and_31339;
  assign concat_31366 = {1'h1, and_31331, priority_sel_2b_2way({~(xbs_fraction[3] | xbs_fraction[2] | nor_31303), and_31331}, 2'h0, {1'h1, ~(xbs_fraction[1] | ~xbs_fraction[0])}, {nor_31304, ~(xbs_fraction[3] | ~xbs_fraction[2])})};
  assign sel_31475 = ~(~and_31343 | and_31362) ? {1'h1, ~(~and_31290 | and_31339) ? concat_31353 : concat_31354} : {and_31343, priority_sel_3b_2way({~(~and_31293 | and_31322), and_31343}, {priority_sel_31344, 1'h0}, concat_31357, {1'h0, priority_sel_31344})};
  assign concat_31374 = {1'h1, and_31282 & and_31335 ? concat_31366 : {1'h0, ~(~and_31282 | and_31335) ? concat_31350 : concat_31351}};
  assign leading_zeroes = and_31343 & and_31362 ? concat_31374 : {1'h0, sel_31475};
  assign cancel_fraction = leading_zeroes >= 5'h1d ? 29'h0000_0000 : {1'h0, xbs_fraction} << leading_zeroes;
  assign cancel_fraction__1 = cancel_fraction[27:1];
  assign carry_fraction__1 = {xbs_fraction[27:2], xbs_fraction[1] | xbs_fraction[0]};
  assign shifted_fraction = carry_bit ? carry_fraction__1 : cancel_fraction__1;
  assign normal_chunk = shifted_fraction[2:0];
  assign fraction_shift__3 = 3'h4;
  assign half_way_chunk = shifted_fraction[3:2];
  assign do_round_up = normal_chunk > fraction_shift__3 | half_way_chunk == 2'h3;
  assign add_31394 = {1'h0, shifted_fraction[26:3]} + {24'h00_0000, do_round_up};
  assign rounding_carry = add_31394[24];
  assign add_31407 = {1'h0, x_bexp} + 9'h001;
  assign sub_31408 = {5'h00, rounding_carry} - {1'h0, leading_zeroes};
  assign fraction_is_zero = add_31217 == 26'h000_0000 & ~(shrl_31204[1] | shrl_31204[2]) & ~(shrl_31204[0] | sticky);
  assign wide_exponent_associative_element = {1'h0, add_31407};
  assign wide_exponent_associative_element__1 = {{4{sub_31408[5]}}, sub_31408};
  assign wide_exponent = wide_exponent_associative_element + wide_exponent_associative_element__1;
  assign wide_exponent__1 = wide_exponent & {10{~fraction_is_zero}};
  assign MAX_EXPONENT = 8'hff;
  assign wide_exponent__2 = wide_exponent__1[8:0] & {9{~wide_exponent__1[9]}};
  assign eq_31423 = x_bexp == MAX_EXPONENT;
  assign eq_31424 = x_fraction == 23'h00_0000;
  assign eq_31425 = y_bexp == MAX_EXPONENT;
  assign eq_31426 = y_fraction == 23'h00_0000;
  assign fraction_shift__2 = 3'h3;
  assign is_operand_inf = eq_31423 & eq_31424 | eq_31425 & eq_31426;
  assign and_reduce_31444 = &wide_exponent__2[7:0];
  assign has_pos_inf = ~(~eq_31423 | ~eq_31424 | x_sign) | ~(~eq_31425 | ~eq_31426 | y_sign);
  assign has_neg_inf = eq_31423 & eq_31424 & x_sign | eq_31425 & eq_31426 & y_sign;
  assign rounded_fraction = {add_31394, normal_chunk};
  assign fraction_shift__1 = rounding_carry ? fraction_shift__3 : fraction_shift__2;
  assign shrl_31457 = rounded_fraction >> fraction_shift__1;
  assign is_result_nan = ~(~eq_31423 | eq_31424) | ~(~eq_31425 | eq_31426) | has_pos_inf & has_neg_inf;
  assign result_sign = priority_sel_1b_2way({add_31217[25], fraction_is_zero}, x_sign & y_sign, ~y_sign, y_sign);
  assign result_fraction = shrl_31457[22:0];
  assign sign_ext_31463 = {23{~(is_operand_inf | wide_exponent__2[8] | and_reduce_31444 | ~((|wide_exponent__2[8:1]) | wide_exponent__2[0]))}};
  assign result_sign__1 = is_operand_inf ? ~has_pos_inf : result_sign;
  assign result_fraction__3 = result_fraction & sign_ext_31463;
  assign FRACTION_HIGH_BIT = 23'h40_0000;
  assign result_sign__2 = ~is_result_nan & result_sign__1;
  assign result_exponent__2 = is_result_nan | is_operand_inf | wide_exponent__2[8] | and_reduce_31444 ? MAX_EXPONENT : wide_exponent__2[7:0];
  assign result_fraction__4 = is_result_nan ? FRACTION_HIGH_BIT : result_fraction__3;
  assign out = {result_sign__2, result_exponent__2, result_fraction__4};
endmodule