module __float32__ldexp(
  input wire [31:0] f,
  input wire [31:0] e,
  output wire [31:0] out
);
  wire [7:0] f_bexp__1;
  wire [7:0] literal_452;
  wire eq_454;
  wire [7:0] add_455;
  wire [22:0] tuple_index_459;
  wire [32:0] e__1;
  wire [22:0] f__1_fraction;
  wire [32:0] MAX_EXPONENT;
  wire [7:0] BIAS;
  wire [32:0] MIN_EXPONENT;
  wire sgt_471;
  wire [7:0] add_472;
  wire [7:0] literal_473;
  wire slt_476;
  wire [7:0] result__2_bexp__1;
  wire eq_482;
  wire eq_483;
  wire f_sign;
  wire nor_491;
  wire [22:0] sel_498;
  wire [31:0] result__5;
  assign f_bexp__1 = f[30:23];
  assign literal_452 = 8'h00;
  assign eq_454 = f_bexp__1 == literal_452;
  assign add_455 = f_bexp__1 + 8'h81;
  assign tuple_index_459 = f[22:0];
  assign e__1 = {{1{e[31]}}, e} + {{25{add_455[7]}}, add_455};
  assign f__1_fraction = tuple_index_459 & {23{~eq_454}};
  assign MAX_EXPONENT = 33'h0_0000_007f;
  assign BIAS = 8'h7f;
  assign MIN_EXPONENT = 33'h1_ffff_ff82;
  assign sgt_471 = $signed(e__1) > $signed(MAX_EXPONENT);
  assign add_472 = e__1[7:0] + BIAS;
  assign literal_473 = 8'hff;
  assign slt_476 = $signed(e__1) < $signed(MIN_EXPONENT);
  assign result__2_bexp__1 = slt_476 ? {7'h00, e__1 == 33'h1_ffff_ff81 & f__1_fraction == 23'h7f_ffff} : (sgt_471 ? literal_473 : add_472);
  assign eq_482 = f_bexp__1 == literal_473;
  assign eq_483 = f__1_fraction == 23'h00_0000;
  assign f_sign = f[31:31];
  assign nor_491 = ~(~eq_482 | eq_483);
  assign sel_498 = nor_491 ? 23'h40_0000 : tuple_index_459 & {23{~(result__2_bexp__1 == literal_452 | slt_476 | sgt_471 | eq_454)}};
  assign result__5 = {~(nor_491 | ~f_sign), nor_491 ? literal_473 : (eq_454 | eq_482 & eq_483 ? f_bexp__1 : result__2_bexp__1), sel_498};
  assign out = result__5;
endmodule