Action bc2faa377880d1f38c83a4b0d6f1f5fedbfad8e28fc8299bcfe8dd99697401a6
Summary
crate:v0.3.0dso:-driver:-
Upstream Dependencies
| Role | Action ID | State | Kind | Subject | Output |
|---|---|---|---|---|---|
verilog_action_id | b74ce59191e9078ccb8c2fce323b1c3d5411de5851333b56d817a059eaa1a030 | done | ir_fn_to_combinational_verilog | ir=fb338f089d8e top=__float32__fma system_verilog=false | verilog_file payload/result.v |
Failure
TIMEOUT(300) docker run exceeded 300 seconds (container=xlsynth-bvc-run-bc2faa377880d1f3-2098204-173)
command:
docker run --name xlsynth-bvc-run-bc2faa377880d1f3-2098204-173 --rm --pull never --network none -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/artifacts/b7/4c/b74ce59191e9078ccb8c2fce323b1c3d5411de5851333b56d817a059eaa1a030/payload/result.v:/inputs/input.v:ro -v /home/cdleary/proj/xlsynth-bvc/flows/yosys_to_aig.ys:/inputs/flow.ys:ro -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/.staging/bc2faa377880d1f38c83a4b0d6f1f5fedbfad8e28fc8299bcfe8dd99697401a6-2098204-1771563412614415631/payload:/outputs -e READ_VERILOG_FLAGS= -e VERILOG_TOP_MODULE_NAME=__float32__fma xlsynth-bvc-yosys-abc:ubuntu24.04 bash -lc
set -euo pipefail
{
echo "read_verilog ${READ_VERILOG_FLAGS} /inputs/input.v"
if [ -n "${VERILOG_TOP_MODULE_NAME:-}" ]; then
echo "hierarchy -check -top ${VERILOG_TOP_MODULE_NAME}"
fi
echo "script /inputs/flow.ys"
echo "write_aiger /outputs/result.aig"
} > /tmp/run.ys
yosys -s /tmp/run.ys
test -s /outputs/result.aig
cleanup: removed timed-out container
stdout:
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.33 (git sha1 2584903a060)
-- Executing script file `/tmp/run.ys' --
1. Executing Verilog-2005 frontend: /inputs/input.v
Parsing Verilog input from `/inputs/input.v' to AST representation.
Generating RTLIL representation for module `\__float32__fma'.
Successfully finished Verilog frontend.
2. Executing HIERARCHY pass (managing design hierarchy).
2.1. Analyzing design hierarchy..
Top module: \__float32__fma
2.2. Analyzing design hierarchy..
Top module: \__float32__fma
Removed 0 unused modules.
-- Executing script file `/inputs/flow.ys' --
3. Executing PROC pass (convert processes to netlists).
3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed 1 dead cases from process $proc$/inputs/input.v:0$544 in module __float32__fma.
Marked 1 switch rules as full_case in process $proc$/inputs/input.v:0$544 in module __float32__fma.
Removed a total of 1 dead cases.
3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 10 assignments to connections.
3.4. Executing PROC_INIT pass (extract init attributes).
3.5. Executing PROC_ARST pass (detect async resets in processes).
3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>
3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\__float32__fma.$proc$/inputs/input.v:0$544'.
1/1: $1\priority_sel_1b_2way$func$/inputs/input.v:273$4.$result[0:0]$552
Creating decoders for process `\__float32__fma.$proc$/inputs/input.v:0$538'.
3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\__float32__fma.\priority_sel_1b_2way$func$/inputs/input.v:273$2.$result' from process `\__float32__fma.$proc$/inputs/input.v:0$544'.
No latch inferred for signal `\__float32__fma.\priority_sel_1b_2way$func$/inputs/input.v:273$4.$result' from process `\__float32__fma.$proc$/inputs/input.v:0$544'.
No latch inferred for signal `\__float32__fma.\priority_sel_1b_2way$func$/inputs/input.v:273$4.sel' from process `\__float32__fma.$proc$/inputs/input.v:0$544'.
No latch inferred for signal `\__float32__fma.\priority_sel_1b_2way$func$/inputs/input.v:273$4.case0' from process `\__float32__fma.$proc$/inputs/input.v:0$544'.
No latch inferred for signal `\__float32__fma.\priority_sel_1b_2way$func$/inputs/input.v:273$4.case1' from process `\__float32__fma.$proc$/inputs/input.v:0$544'.
No latch inferred for signal `\__float32__fma.\priority_sel_1b_2way$func$/inputs/input.v:273$4.default_value' from process `\__float32__fma.$proc$/inputs/input.v:0$544'.
No latch inferred for signal `\__float32__fma.\umul48b_24b_x_24b$func$/inputs/input.v:170$1.$result' from process `\__float32__fma.$proc$/inputs/input.v:0$538'.
No latch inferred for signal `\__float32__fma.\umul48b_24b_x_24b$func$/inputs/input.v:170$3.$result' from process `\__float32__fma.$proc$/inputs/input.v:0$538'.
No latch inferred for signal `\__float32__fma.\umul48b_24b_x_24b$func$/inputs/input.v:170$3.lhs' from process `\__float32__fma.$proc$/inputs/input.v:0$538'.
No latch inferred for signal `\__float32__fma.\umul48b_24b_x_24b$func$/inputs/input.v:170$3.rhs' from process `\__float32__fma.$proc$/inputs/input.v:0$538'.
3.9. Executing PROC_DFF pass (convert process syncs to FFs).
3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\__float32__fma.$proc$/inputs/input.v:0$544'.
Removing empty process `__float32__fma.$proc$/inputs/input.v:0$544'.
Removing empty process `__float32__fma.$proc$/inputs/input.v:0$538'.
Cleaned up 1 empty switch.
3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float32__fma.
<suppressed ~88 debug messages>
4. Executing OPT pass (performing simple optimizations).
4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float32__fma.
4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__float32__fma'.
<suppressed ~24 debug messages>
Removed a total of 8 cells.
4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \__float32__fma..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Replacing known input bits on port B of cell $ternary$/inputs/input.v:200$39: \full_product -> { 1'1 \full_product [46:0] }
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~18 debug messages>
4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \__float32__fma.
Performed a total of 0 changes.
4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__float32__fma'.
Removed a total of 0 cells.
4.6. Executing OPT_DFF pass (perform DFF optimizations).
4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \__float32__fma..
Removed 4 unused cells and 191 unused wires.
<suppressed ~5 debug messages>
4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float32__fma.
4.9. Rerunning OPT passes. (Maybe there is more to do..)
4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \__float32__fma..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~18 debug messages>
4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \__float32__fma.
Performed a total of 0 changes.
4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__float32__fma'.
Removed a total of 0 cells.
4.13. Executing OPT_DFF pass (perform DFF optimizations).
4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \__float32__fma..
4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float32__fma.
4.16. Finished OPT passes. (There is nothing left to do.)
5. Executing TECHMAP pass (map to technology primitives).
5.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
5.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $not.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=9:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=9:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=9:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $eq.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=10:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=10:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=10:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
Running "alumacc" on wrapper $extern:wrap:$le:A_SIGNED=1:A_WIDTH=10:B_SIGNED=1:B_WIDTH=10:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$le:A_SIGNED=1:A_WIDTH=10:B_SIGNED=1:B_WIDTH=10:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$le:A_SIGNED=1:A_WIDTH=10:B_SIGNED=1:B_WIDTH=10:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $xor.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=9:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=9:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=9:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=9:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=9:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=9:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$constmap:63e88c1fc50acae890d5af15bcbdc22c14a0476b$paramod$897ccb31df8b4af74936029641a7903f2547148a\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:f68ea79599d7b8e4299fbea00b5c4918e30bb6b2$paramod$dfc0ab26da2ea9691c13e4b424c315dfa5e3bfa2\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using extmapper simplemap for cells of type $reduce_bool.
Using template $paramod$constmap:18d7277c889af1f131001e6d07d4ed193fab9235$paramod$d6010d514e4d8d68e0a5930a8292758358c67339\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Analyzing pattern of constant bits for this cell:
Constant input on bit 0 of port A: 1'0
Constant input on bit 1 of port A: 1'0
Constant input on bit 2 of port A: 1'0
Constant input on bit 3 of port A: 1'0
Constant input on bit 4 of port A: 1'0
Constant input on bit 5 of port A: 1'0
Constant input on bit 6 of port A: 1'0
Constant input on bit 7 of port A: 1'0
Constant input on bit 8 of port A: 1'0
Constant input on bit 9 of port A: 1'0
Constant input on bit 10 of port A: 1'0
Constant input on bit 11 of port A: 1'0
Constant input on bit 12 of port A: 1'0
Constant input on bit 13 of port A: 1'0
Constant input on bit 14 of port A: 1'0
Constant input on bit 15 of port A: 1'0
Constant input on bit 16 of port A: 1'0
Constant input on bit 17 of port A: 1'0
Constant input on bit 18 of port A: 1'0
Constant input on bit 19 of port A: 1'0
Constant input on bit 20 of port A: 1'0
Constant input on bit 21 of port A: 1'0
Constant input on bit 22 of port A: 1'0
Constant input on bit 23 of port A: 1'0
Constant input on bit 24 of port A: 1'0
Constant input on bit 25 of port A: 1'0
Constant input on bit 26 of port A: 1'0
Constant input on bit 27 of port A: 1'0
Constant input on bit 28 of port A: 1'0
Constant input on bit 29 of port A: 1'0
Constant input on bit 30 of port A: 1'0
Constant input on bit 31 of port A: 1'0
Constant input on bit 32 of port A: 1'0
Constant input on bit 33 of port A: 1'0
Constant input on bit 34 of port A: 1'0
Constant input on bit 35 of port A: 1'0
Constant input on bit 36 of port A: 1'0
Constant input on bit 37 of port A: 1'0
Constant input on bit 38 of port A: 1'0
Constant input on bit 39 of port A: 1'0
Constant input on bit 40 of port A: 1'0
Constant input on bit 41 of port A: 1'0
Constant input on bit 42 of port A: 1'0
Constant input on bit 43 of port A: 1'0
Constant input on bit 44 of port A: 1'0
Constant input on bit 45 of port A: 1'0
Constant input on bit 46 of port A: 1'0
Constant input on bit 47 of port A: 1'0
Constant input on bit 48 of port A: 1'0
Creating constmapped module `$paramod$constmap:a958698cb29c720f26563b1d59e1288525d814a2$paramod$d6010d514e4d8d68e0a5930a8292758358c67339\_90_shift_ops_shr_shl_sshl_sshr'.
5.28. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$constmap:a958698cb29c720f26563b1d59e1288525d814a2$paramod$d6010d514e4d8d68e0a5930a8292758358c67339\_90_shift_ops_shr_shl_sshl_sshr..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
<suppressed ~3297 debug messages>
5.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$constmap:a958698cb29c720f26563b1d59e1288525d814a2$paramod$d6010d514e4d8d68e0a5930a8292758358c67339\_90_shift_ops_shr_shl_sshl_sshr.
<suppressed ~1405 debug messages>
Removed 0 unused cells and 21 unused wires.
Using template $paramod$constmap:a958698cb29c720f26563b1d59e1288525d814a2$paramod$d6010d514e4d8d68e0a5930a8292758358c67339\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Running "alumacc" on wrapper $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=74:Y_WIDTH=74:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=74:Y_WIDTH=74:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=74:Y_WIDTH=74:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=75:B_SIGNED=0:B_WIDTH=75:Y_WIDTH=75:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=75:B_SIGNED=0:B_WIDTH=75:Y_WIDTH=75:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=75:B_SIGNED=0:B_WIDTH=75:Y_WIDTH=75:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $logic_and.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=74:B_SIGNED=0:B_WIDTH=74:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=74:B_SIGNED=0:B_WIDTH=74:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=74:B_SIGNED=0:B_WIDTH=74:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$constmap:57d36aec5230f1b5466bb77295996f43e5ebe03c$paramod$1b2149965d5d414bdb0208f79ff86dccbb1ee5c2\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=25:B_SIGNED=0:B_WIDTH=25:Y_WIDTH=25:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=25:B_SIGNED=0:B_WIDTH=25:Y_WIDTH=25:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=25:B_SIGNED=0:B_WIDTH=25:Y_WIDTH=25:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$gt:A_SIGNED=0:A_WIDTH=49:B_SIGNED=0:B_WIDTH=49:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$gt:A_SIGNED=0:A_WIDTH=49:B_SIGNED=0:B_WIDTH=49:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$gt:A_SIGNED=0:A_WIDTH=49:B_SIGNED=0:B_WIDTH=49:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $reduce_and.
Running "alumacc" on wrapper $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=24:B_SIGNED=0:B_WIDTH=24:Y_WIDTH=48:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=24:B_SIGNED=0:B_WIDTH=24:Y_WIDTH=48:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=24:B_SIGNED=0:B_WIDTH=24:Y_WIDTH=48:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$d629d85c8826a74239b9178d1930215a43b0ceb0\_90_pmux for cells of type $pmux.
Using template $paramod$d2fa05d38998afabc6d4f34471305d0af4b8b2df\_90_alu for cells of type $alu.
Using template $paramod$484d51534650924b7ed4c69e46eed3a56904771f\_90_alu for cells of type $alu.
Using template $paramod$3d4d857737ce5ee764ebe220e87ff73b66d6d0ad\_90_alu for cells of type $alu.
Using template $paramod$8045f2881226ae434b154710c783ad25023f386c\_90_alu for cells of type $alu.
Using template $paramod$00f8ba8a5036a7e9e2cd887da8a12d966d6e77b3\_90_alu for cells of type $alu.
Using template $paramod$98233c12005a3fd580714b9eb133c281de0ab0b8\_90_alu for cells of type $alu.
Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\_90_alu for cells of type $alu.
Using template $paramod$5b6befb72d9e8cb4800d8d538ef0b4af2d21773e\_90_alu for cells of type $alu.
Using template $paramod$4868d58a04723871777326409a611fa912defcd8\_90_alu for cells of type $alu.
Using template $paramod$959c9ddbaba0966d253c0f5ab1a5eabdad847a18\_90_alu for cells of type $alu.
Using extmapper maccmap for cells of type $macc.
add { 1'1 \a [22:0] } * { 1'1 \b [22:0] } (24x24 bits, unsigned)
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001001 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001010 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000001001010 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000001001011 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001000 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000011001 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000110001 for cells of type $lcu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000110000 for cells of type $fa.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000101111 for cells of type $fa.
Using template $paramod$88aad6f8473fb7e4e5fbfb8335ddebad03429eaa\_90_alu for cells of type $alu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000110000 for cells of type $lcu.
No more expansions possible.
<suppressed ~5912 debug messages>
6. Executing ABC pass (technology mapping using ABC).
6.1. Extracting gate netlist of module `\__float32__fma' to `<abc-temp-dir>/input.blif'..
Extracted 21133 gates and 21232 wires to a netlist network with 96 inputs and 32 outputs.
6.1.1. Executing ABC.
stderr:
Attempted Command
docker run --name xlsynth-bvc-run-bc2faa377880d1f3-2098204-173 --rm --pull never --network none -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/artifacts/b7/4c/b74ce59191e9078ccb8c2fce323b1c3d5411de5851333b56d817a059eaa1a030/payload/result.v:/inputs/input.v:ro -v /home/cdleary/proj/xlsynth-bvc/flows/yosys_to_aig.ys:/inputs/flow.ys:ro -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/.staging/bc2faa377880d1f38c83a4b0d6f1f5fedbfad8e28fc8299bcfe8dd99697401a6-2098204-1771563412614415631/payload:/outputs -e READ_VERILOG_FLAGS= -e VERILOG_TOP_MODULE_NAME=__float32__fma xlsynth-bvc-yosys-abc:ubuntu24.04 bash -lc
Action JSON
{
"action": "combo_verilog_to_yosys_abc_aig",
"verilog_action_id": "b74ce59191e9078ccb8c2fce323b1c3d5411de5851333b56d817a059eaa1a030",
"verilog_top_module_name": "__float32__fma",
"yosys_script_ref": {
"path": "flows/yosys_to_aig.ys",
"sha256": "b96ea6e2f96ce4442a7370366c13c8f8a38cfd4e0fcc12860d940d3f0a28b07a"
},
"runtime": {
"docker_image": "xlsynth-bvc-yosys-abc:ubuntu24.04",
"dockerfile": "docker/yosys-abc.Dockerfile"
}
}