module __bfloat16__lt_2(
  input wire [15:0] x,
  input wire [15:0] y,
  output wire out
);
  function automatic priority_sel_1b_3way (input reg [2:0] sel, input reg case0, input reg case1, input reg case2, input reg default_value);
    begin
      casez (sel)
        3'b??1: begin
          priority_sel_1b_3way = case0;
        end
        3'b?10: begin
          priority_sel_1b_3way = case1;
        end
        3'b100: begin
          priority_sel_1b_3way = case2;
        end
        3'b000: begin
          priority_sel_1b_3way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_1b_3way = 1'dx;
        end
      endcase
    end
  endfunction
  wire [7:0] x_bexp__1;
  wire [7:0] literal_687;
  wire [7:0] y_bexp__2;
  wire eq_689;
  wire eq_690;
  wire [6:0] x_fraction__1;
  wire [6:0] y_fraction__1;
  wire [7:0] literal_697;
  wire [6:0] literal_698;
  wire x_sign__2;
  wire y_sign__1;
  wire [6:0] x__1_fraction__2;
  wire [6:0] y__1_fraction__2;
  wire eq_707;
  wire eq_exp;
  wire gt_fraction;
  wire and_711;
  wire and_712;
  wire and_714;
  wire gt_exp;
  wire nor_717;
  wire abs_gt;
  wire and_733;
  wire result;
  wire and_736;
  assign x_bexp__1 = x[14:7];
  assign literal_687 = 8'h00;
  assign y_bexp__2 = y[14:7];
  assign eq_689 = x_bexp__1 == literal_687;
  assign eq_690 = y_bexp__2 == literal_687;
  assign x_fraction__1 = x[6:0];
  assign y_fraction__1 = y[6:0];
  assign literal_697 = 8'hff;
  assign literal_698 = 7'h00;
  assign x_sign__2 = x[15:15];
  assign y_sign__1 = y[15:15];
  assign x__1_fraction__2 = x_fraction__1 & {7{~eq_689}};
  assign y__1_fraction__2 = y_fraction__1 & {7{~eq_690}};
  assign eq_707 = x_sign__2 == y_sign__1;
  assign eq_exp = x_bexp__1 == y_bexp__2;
  assign gt_fraction = x__1_fraction__2 > y__1_fraction__2;
  assign and_711 = x_bexp__1 == literal_697 & x_fraction__1 != literal_698;
  assign and_712 = y_bexp__2 == literal_697 & y_fraction__1 != literal_698;
  assign and_714 = eq_689 & eq_690;
  assign gt_exp = x_bexp__1 > y_bexp__2;
  assign nor_717 = ~(and_711 | and_712);
  assign abs_gt = gt_exp | eq_exp & gt_fraction;
  assign and_733 = ~abs_gt & ~(nor_717 & (eq_707 & eq_exp & x__1_fraction__2 == y__1_fraction__2 | and_714));
  assign result = priority_sel_1b_3way({~(~x_sign__2 | y_sign__1), ~(x_sign__2 | ~y_sign__1), ~(x_sign__2 | y_sign__1)}, abs_gt, 1'h1, 1'h0, and_733);
  assign and_736 = nor_717 & (eq_707 & eq_exp & x_fraction__1 == y_fraction__1 | and_714);
  assign out = ~(and_711 | and_712 | (~and_736 & ~(and_711 | and_712 | ~result) | and_736));
endmodule