module __float32__sub(
  input wire [31:0] x,
  input wire [31:0] y,
  output wire [31:0] out
);
  function automatic [1:0] priority_sel_2b_2way (input reg [1:0] sel, input reg [1:0] case0, input reg [1:0] case1, input reg [1:0] default_value);
    begin
      casez (sel)
        2'b?1: begin
          priority_sel_2b_2way = case0;
        end
        2'b10: begin
          priority_sel_2b_2way = case1;
        end
        2'b00: begin
          priority_sel_2b_2way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_2b_2way = 2'dx;
        end
      endcase
    end
  endfunction
  function automatic [2:0] priority_sel_3b_2way (input reg [1:0] sel, input reg [2:0] case0, input reg [2:0] case1, input reg [2:0] default_value);
    begin
      casez (sel)
        2'b?1: begin
          priority_sel_3b_2way = case0;
        end
        2'b10: begin
          priority_sel_3b_2way = case1;
        end
        2'b00: begin
          priority_sel_3b_2way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_3b_2way = 3'dx;
        end
      endcase
    end
  endfunction
  function automatic priority_sel_1b_2way (input reg [1:0] sel, input reg case0, input reg case1, input reg default_value);
    begin
      casez (sel)
        2'b?1: begin
          priority_sel_1b_2way = case0;
        end
        2'b10: begin
          priority_sel_1b_2way = case1;
        end
        2'b00: begin
          priority_sel_1b_2way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_1b_2way = 1'dx;
        end
      endcase
    end
  endfunction
  wire [7:0] y_bexp__2;
  wire [7:0] x_bexp__2;
  wire [7:0] y__1_bexpnot__1;
  wire [8:0] x_bexp_extended__2;
  wire [8:0] y__1_bexpnot_extended__1;
  wire [8:0] full_result;
  wire overflow_detected;
  wire [22:0] y_fraction__2;
  wire [22:0] tuple_index_31619;
  wire [7:0] x_bexp__3;
  wire [7:0] y_bexp__3;
  wire [22:0] x_fraction__1;
  wire [22:0] y_fraction__3;
  wire nc;
  wire [23:0] fraction_x;
  wire [23:0] fraction_y;
  wire [23:0] sign_ext_31632;
  wire [7:0] narrowed_result;
  wire [7:0] x_bexpor_mask__1;
  wire y_sign__2;
  wire [23:0] fraction_x__1;
  wire [23:0] fraction_y__1;
  wire [2:0] xddend_x__2_squeezed_const_lsb_bits;
  wire [7:0] result;
  wire tuple_index_31642;
  wire [24:0] wide_x_squeezed;
  wire [26:0] wide_y_shift_bits;
  wire [7:0] shift;
  wire [26:0] shrl_31650;
  wire [27:0] shll_31652;
  wire [24:0] xddend_x__2_squeezed;
  wire [25:0] add_31663;
  wire sticky;
  wire [27:0] concat_31669;
  wire [27:0] xbs_fraction__1;
  wire carry_bit;
  wire nor_31710;
  wire nor_31705;
  wire nor_31706;
  wire nor_31696;
  wire nor_31697;
  wire and_31739;
  wire nor_31741;
  wire nor_31743;
  wire and_31736;
  wire nor_31732;
  wire and_31728;
  wire nor_31729;
  wire nor_31723;
  wire nor_31725;
  wire and_31768;
  wire nor_31749;
  wire nor_31750;
  wire and_31789;
  wire [1:0] priority_sel_31790;
  wire and_31785;
  wire and_31781;
  wire and_31777;
  wire [2:0] concat_31803;
  wire [2:0] concat_31800;
  wire [2:0] concat_31799;
  wire [2:0] concat_31797;
  wire [2:0] concat_31796;
  wire and_31808;
  wire [3:0] concat_31812;
  wire [3:0] sel_31924;
  wire [4:0] concat_31820;
  wire [4:0] leading_zeroes;
  wire [28:0] cancel_fraction;
  wire [26:0] cancel_fraction__1;
  wire [26:0] carry_fraction__1;
  wire [26:0] shifted_fraction;
  wire [2:0] normal_chunk;
  wire [2:0] fraction_shift__3;
  wire [1:0] half_way_chunk;
  wire do_round_up;
  wire [24:0] add_31840;
  wire rounding_carry;
  wire [8:0] add_31853;
  wire [5:0] sub_31854;
  wire fraction_is_zero;
  wire [9:0] wide_exponent_associative_element;
  wire [9:0] wide_exponent_associative_element__1;
  wire [9:0] wide_exponent;
  wire [9:0] wide_exponent__1;
  wire [7:0] MAX_EXPONENT;
  wire [8:0] wide_exponent__2;
  wire eq_31869;
  wire eq_31870;
  wire eq_31871;
  wire eq_31872;
  wire x_sign__1;
  wire y_sign__3;
  wire [2:0] fraction_shift__2;
  wire is_operand_inf;
  wire and_reduce_31892;
  wire has_pos_inf;
  wire has_neg_inf;
  wire [27:0] rounded_fraction;
  wire [2:0] fraction_shift__1;
  wire [27:0] shrl_31906;
  wire is_result_nan;
  wire result_sign;
  wire [22:0] result_fraction;
  wire [22:0] sign_ext_31912;
  wire result_sign__1;
  wire [22:0] result_fraction__3;
  wire [22:0] FRACTION_HIGH_BIT;
  wire result_sign__2;
  wire [7:0] result_exponent__2;
  wire [22:0] result_fraction__4;
  assign y_bexp__2 = y[30:23];
  assign x_bexp__2 = x[30:23];
  assign y__1_bexpnot__1 = ~y_bexp__2;
  assign x_bexp_extended__2 = {1'h0, x_bexp__2};
  assign y__1_bexpnot_extended__1 = {1'h0, y__1_bexpnot__1};
  assign full_result = x_bexp_extended__2 + y__1_bexpnot_extended__1;
  assign overflow_detected = full_result[8];
  assign y_fraction__2 = y[22:0];
  assign tuple_index_31619 = x[22:0];
  assign x_bexp__3 = overflow_detected ? x_bexp__2 : y_bexp__2;
  assign y_bexp__3 = overflow_detected ? y_bexp__2 : x_bexp__2;
  assign x_fraction__1 = overflow_detected ? tuple_index_31619 : y_fraction__2;
  assign y_fraction__3 = overflow_detected ? y_fraction__2 : tuple_index_31619;
  assign nc = ~overflow_detected;
  assign fraction_x = {1'h1, x_fraction__1};
  assign fraction_y = {1'h1, y_fraction__3};
  assign sign_ext_31632 = {24{y_bexp__3 != 8'h00}};
  assign narrowed_result = full_result[7:0];
  assign x_bexpor_mask__1 = {8{nc}};
  assign y_sign__2 = y[31:31];
  assign fraction_x__1 = fraction_x & {24{x_bexp__3 != 8'h00}};
  assign fraction_y__1 = fraction_y & sign_ext_31632;
  assign xddend_x__2_squeezed_const_lsb_bits = 3'h0;
  assign result = narrowed_result ^ x_bexpor_mask__1;
  assign tuple_index_31642 = x[31:31];
  assign wide_x_squeezed = {1'h0, fraction_x__1};
  assign wide_y_shift_bits = {fraction_y__1, xddend_x__2_squeezed_const_lsb_bits};
  assign shift = result + {7'h00, overflow_detected};
  assign shrl_31650 = shift >= 8'h1b ? 27'h000_0000 : wide_y_shift_bits >> shift;
  assign shll_31652 = shift >= 8'h1c ? 28'h000_0000 : 28'hfff_ffff << shift;
  assign xddend_x__2_squeezed = tuple_index_31642 ^ ~y_sign__2 ? -wide_x_squeezed : wide_x_squeezed;
  assign add_31663 = {{1{xddend_x__2_squeezed[24]}}, xddend_x__2_squeezed} + {2'h0, shrl_31650[26:3]};
  assign sticky = ~({1'h0, ~y_fraction__3} | ~sign_ext_31632 | shll_31652[26:3]) != 24'h00_0000;
  assign concat_31669 = {add_31663[24:0], shrl_31650[2:1], shrl_31650[0] | sticky};
  assign xbs_fraction__1 = add_31663[25] ? -concat_31669 : concat_31669;
  assign carry_bit = xbs_fraction__1[27];
  assign nor_31710 = ~(xbs_fraction__1[25] | xbs_fraction__1[24]);
  assign nor_31705 = ~(xbs_fraction__1[17] | xbs_fraction__1[16]);
  assign nor_31706 = ~(xbs_fraction__1[19] | xbs_fraction__1[18]);
  assign nor_31696 = ~(xbs_fraction__1[9] | xbs_fraction__1[8]);
  assign nor_31697 = ~(xbs_fraction__1[11] | xbs_fraction__1[10]);
  assign and_31739 = ~(carry_bit | xbs_fraction__1[26]) & nor_31710;
  assign nor_31741 = ~(xbs_fraction__1[21] | xbs_fraction__1[20]);
  assign nor_31743 = ~(carry_bit | ~xbs_fraction__1[26]);
  assign and_31736 = nor_31706 & nor_31705;
  assign nor_31732 = ~(xbs_fraction__1[13] | xbs_fraction__1[12]);
  assign and_31728 = nor_31697 & nor_31696;
  assign nor_31729 = ~(xbs_fraction__1[11] | ~xbs_fraction__1[10]);
  assign nor_31723 = ~(xbs_fraction__1[5] | xbs_fraction__1[4]);
  assign nor_31725 = ~(xbs_fraction__1[7] | xbs_fraction__1[6]);
  assign and_31768 = ~(xbs_fraction__1[23] | xbs_fraction__1[22]) & nor_31741;
  assign nor_31749 = ~(xbs_fraction__1[1] | xbs_fraction__1[0]);
  assign nor_31750 = ~(xbs_fraction__1[3] | xbs_fraction__1[2]);
  assign and_31789 = and_31739 & and_31768;
  assign priority_sel_31790 = priority_sel_2b_2way({~(carry_bit | xbs_fraction__1[26] | nor_31710), and_31739}, {nor_31743, 1'h0}, {1'h1, ~(xbs_fraction__1[25] | ~xbs_fraction__1[24])}, {1'h0, nor_31743});
  assign and_31785 = ~(xbs_fraction__1[15] | xbs_fraction__1[14]) & nor_31732;
  assign and_31781 = nor_31725 & nor_31723;
  assign and_31777 = nor_31750 & nor_31749;
  assign concat_31803 = {1'h1, ~(xbs_fraction__1[23] | xbs_fraction__1[22] | nor_31741) ? {1'h1, ~(xbs_fraction__1[21] | ~xbs_fraction__1[20])} : {1'h0, ~(xbs_fraction__1[23] | ~xbs_fraction__1[22])}};
  assign concat_31800 = {and_31736, priority_sel_2b_2way({~(xbs_fraction__1[19] | xbs_fraction__1[18] | nor_31705), and_31736}, 2'h0, {1'h1, ~(xbs_fraction__1[17] | ~xbs_fraction__1[16])}, {nor_31706, ~(xbs_fraction__1[19] | ~xbs_fraction__1[18])})};
  assign concat_31799 = {1'h1, ~(xbs_fraction__1[15] | xbs_fraction__1[14] | nor_31732) ? {1'h1, ~(xbs_fraction__1[13] | ~xbs_fraction__1[12])} : {1'h0, ~(xbs_fraction__1[15] | ~xbs_fraction__1[14])}};
  assign concat_31797 = {and_31728, priority_sel_2b_2way({~(xbs_fraction__1[11] | xbs_fraction__1[10] | nor_31696), and_31728}, {nor_31729, 1'h0}, {1'h1, ~(xbs_fraction__1[9] | ~xbs_fraction__1[8])}, {nor_31697, nor_31729})};
  assign concat_31796 = {1'h1, ~(xbs_fraction__1[7] | xbs_fraction__1[6] | nor_31723) ? {1'h1, ~(xbs_fraction__1[5] | ~xbs_fraction__1[4])} : {nor_31725, ~(xbs_fraction__1[7] | ~xbs_fraction__1[6])}};
  assign and_31808 = and_31736 & and_31785;
  assign concat_31812 = {1'h1, and_31777, priority_sel_2b_2way({~(xbs_fraction__1[3] | xbs_fraction__1[2] | nor_31749), and_31777}, 2'h0, {1'h1, ~(xbs_fraction__1[1] | ~xbs_fraction__1[0])}, {nor_31750, ~(xbs_fraction__1[3] | ~xbs_fraction__1[2])})};
  assign sel_31924 = ~(~and_31789 | and_31808) ? {1'h1, ~(~and_31736 | and_31785) ? concat_31799 : concat_31800} : {and_31789, priority_sel_3b_2way({~(~and_31739 | and_31768), and_31789}, {priority_sel_31790, 1'h0}, concat_31803, {1'h0, priority_sel_31790})};
  assign concat_31820 = {1'h1, and_31728 & and_31781 ? concat_31812 : {1'h0, ~(~and_31728 | and_31781) ? concat_31796 : concat_31797}};
  assign leading_zeroes = and_31789 & and_31808 ? concat_31820 : {1'h0, sel_31924};
  assign cancel_fraction = leading_zeroes >= 5'h1d ? 29'h0000_0000 : {1'h0, xbs_fraction__1} << leading_zeroes;
  assign cancel_fraction__1 = cancel_fraction[27:1];
  assign carry_fraction__1 = {xbs_fraction__1[27:2], xbs_fraction__1[1] | xbs_fraction__1[0]};
  assign shifted_fraction = carry_bit ? carry_fraction__1 : cancel_fraction__1;
  assign normal_chunk = shifted_fraction[2:0];
  assign fraction_shift__3 = 3'h4;
  assign half_way_chunk = shifted_fraction[3:2];
  assign do_round_up = normal_chunk > fraction_shift__3 | half_way_chunk == 2'h3;
  assign add_31840 = {1'h0, shifted_fraction[26:3]} + {24'h00_0000, do_round_up};
  assign rounding_carry = add_31840[24];
  assign add_31853 = {1'h0, x_bexp__3} + 9'h001;
  assign sub_31854 = {5'h00, rounding_carry} - {1'h0, leading_zeroes};
  assign fraction_is_zero = add_31663 == 26'h000_0000 & ~(shrl_31650[1] | shrl_31650[2]) & ~(shrl_31650[0] | sticky);
  assign wide_exponent_associative_element = {1'h0, add_31853};
  assign wide_exponent_associative_element__1 = {{4{sub_31854[5]}}, sub_31854};
  assign wide_exponent = wide_exponent_associative_element + wide_exponent_associative_element__1;
  assign wide_exponent__1 = wide_exponent & {10{~fraction_is_zero}};
  assign MAX_EXPONENT = 8'hff;
  assign wide_exponent__2 = wide_exponent__1[8:0] & {9{~wide_exponent__1[9]}};
  assign eq_31869 = x_bexp__3 == MAX_EXPONENT;
  assign eq_31870 = x_fraction__1 == 23'h00_0000;
  assign eq_31871 = y_bexp__3 == MAX_EXPONENT;
  assign eq_31872 = y_fraction__3 == 23'h00_0000;
  assign x_sign__1 = overflow_detected ? tuple_index_31642 : ~y_sign__2;
  assign y_sign__3 = overflow_detected ? ~y_sign__2 : tuple_index_31642;
  assign fraction_shift__2 = 3'h3;
  assign is_operand_inf = eq_31869 & eq_31870 | eq_31871 & eq_31872;
  assign and_reduce_31892 = &wide_exponent__2[7:0];
  assign has_pos_inf = ~(~eq_31869 | ~eq_31870 | x_sign__1) | ~(~eq_31871 | ~eq_31872 | y_sign__3);
  assign has_neg_inf = eq_31869 & eq_31870 & x_sign__1 | eq_31871 & eq_31872 & y_sign__3;
  assign rounded_fraction = {add_31840, normal_chunk};
  assign fraction_shift__1 = rounding_carry ? fraction_shift__3 : fraction_shift__2;
  assign shrl_31906 = rounded_fraction >> fraction_shift__1;
  assign is_result_nan = ~(~eq_31869 | eq_31870) | ~(~eq_31871 | eq_31872) | has_pos_inf & has_neg_inf;
  assign result_sign = priority_sel_1b_2way({add_31663[25], fraction_is_zero}, ~(~tuple_index_31642 | y_sign__2), ~y_sign__3, y_sign__3);
  assign result_fraction = shrl_31906[22:0];
  assign sign_ext_31912 = {23{~(is_operand_inf | wide_exponent__2[8] | and_reduce_31892 | ~((|wide_exponent__2[8:1]) | wide_exponent__2[0]))}};
  assign result_sign__1 = is_operand_inf ? ~has_pos_inf : result_sign;
  assign result_fraction__3 = result_fraction & sign_ext_31912;
  assign FRACTION_HIGH_BIT = 23'h40_0000;
  assign result_sign__2 = ~is_result_nan & result_sign__1;
  assign result_exponent__2 = is_result_nan | is_operand_inf | wide_exponent__2[8] | and_reduce_31892 ? MAX_EXPONENT : wide_exponent__2[7:0];
  assign result_fraction__4 = is_result_nan ? FRACTION_HIGH_BIT : result_fraction__3;
  assign out = {result_sign__2, result_exponent__2, result_fraction__4};
endmodule