module __float32__add(
  input wire [31:0] x,
  input wire [31:0] y,
  output wire [31:0] out
);
  function automatic [1:0] priority_sel_2b_2way (input reg [1:0] sel, input reg [1:0] case0, input reg [1:0] case1, input reg [1:0] default_value);
    begin
      casez (sel)
        2'b?1: begin
          priority_sel_2b_2way = case0;
        end
        2'b10: begin
          priority_sel_2b_2way = case1;
        end
        2'b00: begin
          priority_sel_2b_2way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_2b_2way = 2'dx;
        end
      endcase
    end
  endfunction
  function automatic [2:0] priority_sel_3b_2way (input reg [1:0] sel, input reg [2:0] case0, input reg [2:0] case1, input reg [2:0] default_value);
    begin
      casez (sel)
        2'b?1: begin
          priority_sel_3b_2way = case0;
        end
        2'b10: begin
          priority_sel_3b_2way = case1;
        end
        2'b00: begin
          priority_sel_3b_2way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_3b_2way = 3'dx;
        end
      endcase
    end
  endfunction
  function automatic priority_sel_1b_2way (input reg [1:0] sel, input reg case0, input reg case1, input reg default_value);
    begin
      casez (sel)
        2'b?1: begin
          priority_sel_1b_2way = case0;
        end
        2'b10: begin
          priority_sel_1b_2way = case1;
        end
        2'b00: begin
          priority_sel_1b_2way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_1b_2way = 1'dx;
        end
      endcase
    end
  endfunction
  wire [7:0] y_bexp__1;
  wire [7:0] x_bexp__1;
  wire [7:0] y_bexpnot;
  wire [8:0] x_bexp_extended__1;
  wire [8:0] y_bexpnot_extended;
  wire [8:0] full_result;
  wire overflow_detected;
  wire [22:0] tuple_index_31175;
  wire [22:0] tuple_index_31176;
  wire [7:0] x_bexp;
  wire [7:0] y_bexp;
  wire [22:0] x_fraction;
  wire [22:0] y_fraction;
  wire nc;
  wire [23:0] fraction_x;
  wire [23:0] fraction_y;
  wire [23:0] sign_ext_31189;
  wire [7:0] narrowed_result;
  wire [7:0] x_bexpor_mask;
  wire [23:0] fraction_x__1;
  wire [23:0] fraction_y__1;
  wire [2:0] xddend_x__1_squeezed_const_lsb_bits;
  wire [7:0] result;
  wire tuple_index_31198;
  wire tuple_index_31199;
  wire [24:0] wide_x_squeezed;
  wire [26:0] wide_y_shift_bits;
  wire [7:0] shift;
  wire [26:0] shrl_31206;
  wire [27:0] shll_31208;
  wire [24:0] xddend_x__1_squeezed;
  wire [25:0] add_31219;
  wire sticky;
  wire [27:0] concat_31225;
  wire [27:0] xbs_fraction;
  wire carry_bit;
  wire nor_31266;
  wire nor_31261;
  wire nor_31262;
  wire nor_31252;
  wire nor_31253;
  wire and_31295;
  wire nor_31297;
  wire nor_31299;
  wire and_31292;
  wire nor_31288;
  wire and_31284;
  wire nor_31285;
  wire nor_31279;
  wire nor_31281;
  wire and_31324;
  wire nor_31305;
  wire nor_31306;
  wire and_31345;
  wire [1:0] priority_sel_31346;
  wire and_31341;
  wire and_31337;
  wire and_31333;
  wire [2:0] concat_31359;
  wire [2:0] concat_31356;
  wire [2:0] concat_31355;
  wire [2:0] concat_31353;
  wire [2:0] concat_31352;
  wire and_31364;
  wire [3:0] concat_31368;
  wire [3:0] sel_31479;
  wire [4:0] concat_31376;
  wire [4:0] leading_zeroes;
  wire [28:0] cancel_fraction;
  wire [26:0] cancel_fraction__1;
  wire [26:0] carry_fraction__1;
  wire [26:0] shifted_fraction;
  wire [2:0] normal_chunk;
  wire [2:0] fraction_shift__3;
  wire [1:0] half_way_chunk;
  wire do_round_up;
  wire [24:0] add_31396;
  wire rounding_carry;
  wire [8:0] add_31409;
  wire [5:0] sub_31410;
  wire fraction_is_zero;
  wire [9:0] wide_exponent_associative_element;
  wire [9:0] wide_exponent_associative_element__1;
  wire [9:0] wide_exponent;
  wire [9:0] wide_exponent__1;
  wire [7:0] MAX_EXPONENT;
  wire [8:0] wide_exponent__2;
  wire eq_31425;
  wire eq_31426;
  wire eq_31427;
  wire eq_31428;
  wire x_sign;
  wire y_sign;
  wire [2:0] fraction_shift__2;
  wire is_operand_inf;
  wire and_reduce_31448;
  wire has_pos_inf;
  wire has_neg_inf;
  wire [27:0] rounded_fraction;
  wire [2:0] fraction_shift__1;
  wire [27:0] shrl_31461;
  wire is_result_nan;
  wire result_sign;
  wire [22:0] result_fraction;
  wire [22:0] sign_ext_31467;
  wire result_sign__1;
  wire [22:0] result_fraction__3;
  wire [22:0] FRACTION_HIGH_BIT;
  wire result_sign__2;
  wire [7:0] result_exponent__2;
  wire [22:0] result_fraction__4;
  assign y_bexp__1 = y[30:23];
  assign x_bexp__1 = x[30:23];
  assign y_bexpnot = ~y_bexp__1;
  assign x_bexp_extended__1 = {1'h0, x_bexp__1};
  assign y_bexpnot_extended = {1'h0, y_bexpnot};
  assign full_result = x_bexp_extended__1 + y_bexpnot_extended;
  assign overflow_detected = full_result[8];
  assign tuple_index_31175 = y[22:0];
  assign tuple_index_31176 = x[22:0];
  assign x_bexp = overflow_detected ? x_bexp__1 : y_bexp__1;
  assign y_bexp = overflow_detected ? y_bexp__1 : x_bexp__1;
  assign x_fraction = overflow_detected ? tuple_index_31176 : tuple_index_31175;
  assign y_fraction = overflow_detected ? tuple_index_31175 : tuple_index_31176;
  assign nc = ~overflow_detected;
  assign fraction_x = {1'h1, x_fraction};
  assign fraction_y = {1'h1, y_fraction};
  assign sign_ext_31189 = {24{y_bexp != 8'h00}};
  assign narrowed_result = full_result[7:0];
  assign x_bexpor_mask = {8{nc}};
  assign fraction_x__1 = fraction_x & {24{x_bexp != 8'h00}};
  assign fraction_y__1 = fraction_y & sign_ext_31189;
  assign xddend_x__1_squeezed_const_lsb_bits = 3'h0;
  assign result = narrowed_result ^ x_bexpor_mask;
  assign tuple_index_31198 = x[31:31];
  assign tuple_index_31199 = y[31:31];
  assign wide_x_squeezed = {1'h0, fraction_x__1};
  assign wide_y_shift_bits = {fraction_y__1, xddend_x__1_squeezed_const_lsb_bits};
  assign shift = result + {7'h00, overflow_detected};
  assign shrl_31206 = shift >= 8'h1b ? 27'h000_0000 : wide_y_shift_bits >> shift;
  assign shll_31208 = shift >= 8'h1c ? 28'h000_0000 : 28'hfff_ffff << shift;
  assign xddend_x__1_squeezed = tuple_index_31198 ^ tuple_index_31199 ? -wide_x_squeezed : wide_x_squeezed;
  assign add_31219 = {{1{xddend_x__1_squeezed[24]}}, xddend_x__1_squeezed} + {2'h0, shrl_31206[26:3]};
  assign sticky = ~({1'h0, ~y_fraction} | ~sign_ext_31189 | shll_31208[26:3]) != 24'h00_0000;
  assign concat_31225 = {add_31219[24:0], shrl_31206[2:1], shrl_31206[0] | sticky};
  assign xbs_fraction = add_31219[25] ? -concat_31225 : concat_31225;
  assign carry_bit = xbs_fraction[27];
  assign nor_31266 = ~(xbs_fraction[25] | xbs_fraction[24]);
  assign nor_31261 = ~(xbs_fraction[17] | xbs_fraction[16]);
  assign nor_31262 = ~(xbs_fraction[19] | xbs_fraction[18]);
  assign nor_31252 = ~(xbs_fraction[9] | xbs_fraction[8]);
  assign nor_31253 = ~(xbs_fraction[11] | xbs_fraction[10]);
  assign and_31295 = ~(carry_bit | xbs_fraction[26]) & nor_31266;
  assign nor_31297 = ~(xbs_fraction[21] | xbs_fraction[20]);
  assign nor_31299 = ~(carry_bit | ~xbs_fraction[26]);
  assign and_31292 = nor_31262 & nor_31261;
  assign nor_31288 = ~(xbs_fraction[13] | xbs_fraction[12]);
  assign and_31284 = nor_31253 & nor_31252;
  assign nor_31285 = ~(xbs_fraction[11] | ~xbs_fraction[10]);
  assign nor_31279 = ~(xbs_fraction[5] | xbs_fraction[4]);
  assign nor_31281 = ~(xbs_fraction[7] | xbs_fraction[6]);
  assign and_31324 = ~(xbs_fraction[23] | xbs_fraction[22]) & nor_31297;
  assign nor_31305 = ~(xbs_fraction[1] | xbs_fraction[0]);
  assign nor_31306 = ~(xbs_fraction[3] | xbs_fraction[2]);
  assign and_31345 = and_31295 & and_31324;
  assign priority_sel_31346 = priority_sel_2b_2way({~(carry_bit | xbs_fraction[26] | nor_31266), and_31295}, {nor_31299, 1'h0}, {1'h1, ~(xbs_fraction[25] | ~xbs_fraction[24])}, {1'h0, nor_31299});
  assign and_31341 = ~(xbs_fraction[15] | xbs_fraction[14]) & nor_31288;
  assign and_31337 = nor_31281 & nor_31279;
  assign and_31333 = nor_31306 & nor_31305;
  assign concat_31359 = {1'h1, ~(xbs_fraction[23] | xbs_fraction[22] | nor_31297) ? {1'h1, ~(xbs_fraction[21] | ~xbs_fraction[20])} : {1'h0, ~(xbs_fraction[23] | ~xbs_fraction[22])}};
  assign concat_31356 = {and_31292, priority_sel_2b_2way({~(xbs_fraction[19] | xbs_fraction[18] | nor_31261), and_31292}, 2'h0, {1'h1, ~(xbs_fraction[17] | ~xbs_fraction[16])}, {nor_31262, ~(xbs_fraction[19] | ~xbs_fraction[18])})};
  assign concat_31355 = {1'h1, ~(xbs_fraction[15] | xbs_fraction[14] | nor_31288) ? {1'h1, ~(xbs_fraction[13] | ~xbs_fraction[12])} : {1'h0, ~(xbs_fraction[15] | ~xbs_fraction[14])}};
  assign concat_31353 = {and_31284, priority_sel_2b_2way({~(xbs_fraction[11] | xbs_fraction[10] | nor_31252), and_31284}, {nor_31285, 1'h0}, {1'h1, ~(xbs_fraction[9] | ~xbs_fraction[8])}, {nor_31253, nor_31285})};
  assign concat_31352 = {1'h1, ~(xbs_fraction[7] | xbs_fraction[6] | nor_31279) ? {1'h1, ~(xbs_fraction[5] | ~xbs_fraction[4])} : {nor_31281, ~(xbs_fraction[7] | ~xbs_fraction[6])}};
  assign and_31364 = and_31292 & and_31341;
  assign concat_31368 = {1'h1, and_31333, priority_sel_2b_2way({~(xbs_fraction[3] | xbs_fraction[2] | nor_31305), and_31333}, 2'h0, {1'h1, ~(xbs_fraction[1] | ~xbs_fraction[0])}, {nor_31306, ~(xbs_fraction[3] | ~xbs_fraction[2])})};
  assign sel_31479 = ~(~and_31345 | and_31364) ? {1'h1, ~(~and_31292 | and_31341) ? concat_31355 : concat_31356} : {and_31345, priority_sel_3b_2way({~(~and_31295 | and_31324), and_31345}, {priority_sel_31346, 1'h0}, concat_31359, {1'h0, priority_sel_31346})};
  assign concat_31376 = {1'h1, and_31284 & and_31337 ? concat_31368 : {1'h0, ~(~and_31284 | and_31337) ? concat_31352 : concat_31353}};
  assign leading_zeroes = and_31345 & and_31364 ? concat_31376 : {1'h0, sel_31479};
  assign cancel_fraction = leading_zeroes >= 5'h1d ? 29'h0000_0000 : {1'h0, xbs_fraction} << leading_zeroes;
  assign cancel_fraction__1 = cancel_fraction[27:1];
  assign carry_fraction__1 = {xbs_fraction[27:2], xbs_fraction[1] | xbs_fraction[0]};
  assign shifted_fraction = carry_bit ? carry_fraction__1 : cancel_fraction__1;
  assign normal_chunk = shifted_fraction[2:0];
  assign fraction_shift__3 = 3'h4;
  assign half_way_chunk = shifted_fraction[3:2];
  assign do_round_up = normal_chunk > fraction_shift__3 | half_way_chunk == 2'h3;
  assign add_31396 = {1'h0, shifted_fraction[26:3]} + {24'h00_0000, do_round_up};
  assign rounding_carry = add_31396[24];
  assign add_31409 = {1'h0, x_bexp} + 9'h001;
  assign sub_31410 = {5'h00, rounding_carry} - {1'h0, leading_zeroes};
  assign fraction_is_zero = add_31219 == 26'h000_0000 & ~(shrl_31206[1] | shrl_31206[2]) & ~(shrl_31206[0] | sticky);
  assign wide_exponent_associative_element = {1'h0, add_31409};
  assign wide_exponent_associative_element__1 = {{4{sub_31410[5]}}, sub_31410};
  assign wide_exponent = wide_exponent_associative_element + wide_exponent_associative_element__1;
  assign wide_exponent__1 = wide_exponent & {10{~fraction_is_zero}};
  assign MAX_EXPONENT = 8'hff;
  assign wide_exponent__2 = wide_exponent__1[8:0] & {9{~wide_exponent__1[9]}};
  assign eq_31425 = x_bexp == MAX_EXPONENT;
  assign eq_31426 = x_fraction == 23'h00_0000;
  assign eq_31427 = y_bexp == MAX_EXPONENT;
  assign eq_31428 = y_fraction == 23'h00_0000;
  assign x_sign = overflow_detected ? tuple_index_31198 : tuple_index_31199;
  assign y_sign = overflow_detected ? tuple_index_31199 : tuple_index_31198;
  assign fraction_shift__2 = 3'h3;
  assign is_operand_inf = eq_31425 & eq_31426 | eq_31427 & eq_31428;
  assign and_reduce_31448 = &wide_exponent__2[7:0];
  assign has_pos_inf = ~(~eq_31425 | ~eq_31426 | x_sign) | ~(~eq_31427 | ~eq_31428 | y_sign);
  assign has_neg_inf = eq_31425 & eq_31426 & x_sign | eq_31427 & eq_31428 & y_sign;
  assign rounded_fraction = {add_31396, normal_chunk};
  assign fraction_shift__1 = rounding_carry ? fraction_shift__3 : fraction_shift__2;
  assign shrl_31461 = rounded_fraction >> fraction_shift__1;
  assign is_result_nan = ~(~eq_31425 | eq_31426) | ~(~eq_31427 | eq_31428) | has_pos_inf & has_neg_inf;
  assign result_sign = priority_sel_1b_2way({add_31219[25], fraction_is_zero}, tuple_index_31198 & tuple_index_31199, ~y_sign, y_sign);
  assign result_fraction = shrl_31461[22:0];
  assign sign_ext_31467 = {23{~(is_operand_inf | wide_exponent__2[8] | and_reduce_31448 | ~((|wide_exponent__2[8:1]) | wide_exponent__2[0]))}};
  assign result_sign__1 = is_operand_inf ? ~has_pos_inf : result_sign;
  assign result_fraction__3 = result_fraction & sign_ext_31467;
  assign FRACTION_HIGH_BIT = 23'h40_0000;
  assign result_sign__2 = ~is_result_nan & result_sign__1;
  assign result_exponent__2 = is_result_nan | is_operand_inf | wide_exponent__2[8] | and_reduce_31448 ? MAX_EXPONENT : wide_exponent__2[7:0];
  assign result_fraction__4 = is_result_nan ? FRACTION_HIGH_BIT : result_fraction__3;
  assign out = {result_sign__2, result_exponent__2, result_fraction__4};
endmodule