module __float64__sub( input wire [63:0] x, input wire [63:0] y, output wire [63:0] out ); function automatic priority_sel_1b_2way (input reg [1:0] sel, input reg case0, input reg case1, input reg default_value); begin casez (sel) 2'b?1: begin priority_sel_1b_2way = case0; end 2'b10: begin priority_sel_1b_2way = case1; end 2'b00: begin priority_sel_1b_2way = default_value; end default: begin // Propagate X priority_sel_1b_2way = 1'dx; end endcase end endfunction function automatic [1:0] priority_sel_2b_2way (input reg [1:0] sel, input reg [1:0] case0, input reg [1:0] case1, input reg [1:0] default_value); begin casez (sel) 2'b?1: begin priority_sel_2b_2way = case0; end 2'b10: begin priority_sel_2b_2way = case1; end 2'b00: begin priority_sel_2b_2way = default_value; end default: begin // Propagate X priority_sel_2b_2way = 2'dx; end endcase end endfunction function automatic priority_sel_1b_4way (input reg [3:0] sel, input reg case0, input reg case1, input reg case2, input reg case3, input reg default_value); begin casez (sel) 4'b???1: begin priority_sel_1b_4way = case0; end 4'b??10: begin priority_sel_1b_4way = case1; end 4'b?100: begin priority_sel_1b_4way = case2; end 4'b1000: begin priority_sel_1b_4way = case3; end 4'b0000: begin priority_sel_1b_4way = default_value; end default: begin // Propagate X priority_sel_1b_4way = 1'dx; end endcase end endfunction function automatic [2:0] priority_sel_3b_2way (input reg [1:0] sel, input reg [2:0] case0, input reg [2:0] case1, input reg [2:0] default_value); begin casez (sel) 2'b?1: begin priority_sel_3b_2way = case0; end 2'b10: begin priority_sel_3b_2way = case1; end 2'b00: begin priority_sel_3b_2way = default_value; end default: begin // Propagate X priority_sel_3b_2way = 3'dx; end endcase end endfunction function automatic [3:0] priority_sel_4b_2way (input reg [1:0] sel, input reg [3:0] case0, input reg [3:0] case1, input reg [3:0] default_value); begin casez (sel) 2'b?1: begin priority_sel_4b_2way = case0; end 2'b10: begin priority_sel_4b_2way = case1; end 2'b00: begin priority_sel_4b_2way = default_value; end default: begin // Propagate X priority_sel_4b_2way = 4'dx; end endcase end endfunction function automatic [4:0] priority_sel_5b_2way (input reg [1:0] sel, input reg [4:0] case0, input reg [4:0] case1, input reg [4:0] default_value); begin casez (sel) 2'b?1: begin priority_sel_5b_2way = case0; end 2'b10: begin priority_sel_5b_2way = case1; end 2'b00: begin priority_sel_5b_2way = default_value; end default: begin // Propagate X priority_sel_5b_2way = 5'dx; end endcase end endfunction wire [10:0] y_bexp__2; wire [10:0] x_bexp__2; wire [10:0] y__1_bexpnot__1; wire [11:0] x_bexp_extended__2; wire [11:0] y__1_bexpnot_extended__1; wire [11:0] full_result; wire overflow_detected; wire [51:0] y_fraction__2; wire [51:0] tuple_index_33630; wire [10:0] x_bexp__3; wire [10:0] y_bexp__3; wire [51:0] x_fraction__1; wire [51:0] y_fraction__3; wire nc; wire [52:0] fraction_x; wire [52:0] fraction_y; wire [52:0] sign_ext_33643; wire [10:0] narrowed_result; wire [10:0] x_bexpor_mask__1; wire y_sign__2; wire [52:0] fraction_x__1; wire [52:0] fraction_y__1; wire [2:0] xddend_x__2_squeezed_const_lsb_bits; wire [10:0] result; wire tuple_index_33653; wire [53:0] wide_x_squeezed; wire [55:0] wide_y_shift_bits; wire [10:0] shift; wire [55:0] shrl_33661; wire [56:0] shll_33663; wire [53:0] xddend_x__2_squeezed; wire [54:0] add_33674; wire sticky; wire [56:0] concat_33680; wire [56:0] xbs_fraction__1; wire nor_33693; wire nor_33699; wire and_33724; wire nor_33726; wire carry_bit; wire and_33734; wire nor_33736; wire and_33775; wire nor_33776; wire nor_33778; wire and_33785; wire nor_33786; wire nor_33788; wire nor_33762; wire nor_33763; wire nor_33768; wire nor_33769; wire nor_33758; wire nor_33759; wire nor_33749; wire nor_33750; wire nor_33819; wire nor_33820; wire and_33822; wire nor_33823; wire nor_33830; wire nor_33831; wire and_33833; wire nor_33834; wire and_33810; wire nor_33812; wire and_33815; wire nor_33816; wire and_33807; wire nor_33808; wire nor_33802; wire nor_33804; wire and_33798; wire nor_33799; wire nor_33793; wire nor_33795; wire and_33863; wire and_33864; wire and_33866; wire and_33867; wire and_33875; wire and_33876; wire and_33878; wire and_33879; wire and_33899; wire nor_33901; wire priority_sel_33909; wire and_33911; wire nor_33913; wire priority_sel_33921; wire and_33896; wire [1:0] priority_sel_33897; wire and_33892; wire and_33888; wire [2:0] concat_33944; wire [2:0] concat_33956; wire [2:0] concat_33932; wire [2:0] concat_33929; wire [2:0] concat_33928; wire [2:0] concat_33926; wire [2:0] concat_33925; wire and_33965; wire and_33971; wire and_33962; wire [2:0] fraction_shift__3; wire and_33992; wire [3:0] priority_sel_33993; wire [3:0] priority_sel_33994; wire [3:0] sel_34109; wire [4:0] concat_33996; wire [5:0] leading_zeroes; wire [57:0] cancel_fraction; wire [55:0] cancel_fraction__1; wire [55:0] carry_fraction__1; wire [55:0] shifted_fraction; wire [2:0] normal_chunk; wire [1:0] half_way_chunk; wire do_round_up; wire [53:0] add_34024; wire rounding_carry; wire [11:0] add_34037; wire [6:0] sub_34038; wire fraction_is_zero; wire [12:0] wide_exponent_associative_element; wire [12:0] wide_exponent_associative_element__1; wire [12:0] wide_exponent; wire [12:0] wide_exponent__1; wire [10:0] MAX_EXPONENT; wire [11:0] wide_exponent__2; wire eq_34053; wire eq_34054; wire eq_34055; wire eq_34056; wire x_sign__1; wire y_sign__3; wire [2:0] fraction_shift__2; wire is_operand_inf; wire and_reduce_34076; wire has_pos_inf; wire has_neg_inf; wire [56:0] rounded_fraction; wire [2:0] fraction_shift__1; wire [56:0] shrl_34090; wire is_result_nan; wire result_sign; wire [51:0] result_fraction; wire [51:0] sign_ext_34096; wire result_sign__1; wire [51:0] result_fraction__3; wire [51:0] FRACTION_HIGH_BIT; wire result_sign__2; wire [10:0] result_exponent__2; wire [51:0] result_fraction__4; assign y_bexp__2 = y[62:52]; assign x_bexp__2 = x[62:52]; assign y__1_bexpnot__1 = ~y_bexp__2; assign x_bexp_extended__2 = {1'h0, x_bexp__2}; assign y__1_bexpnot_extended__1 = {1'h0, y__1_bexpnot__1}; assign full_result = x_bexp_extended__2 + y__1_bexpnot_extended__1; assign overflow_detected = full_result[11]; assign y_fraction__2 = y[51:0]; assign tuple_index_33630 = x[51:0]; assign x_bexp__3 = overflow_detected ? x_bexp__2 : y_bexp__2; assign y_bexp__3 = overflow_detected ? y_bexp__2 : x_bexp__2; assign x_fraction__1 = overflow_detected ? tuple_index_33630 : y_fraction__2; assign y_fraction__3 = overflow_detected ? y_fraction__2 : tuple_index_33630; assign nc = ~overflow_detected; assign fraction_x = {1'h1, x_fraction__1}; assign fraction_y = {1'h1, y_fraction__3}; assign sign_ext_33643 = {53{y_bexp__3 != 11'h000}}; assign narrowed_result = full_result[10:0]; assign x_bexpor_mask__1 = {11{nc}}; assign y_sign__2 = y[63:63]; assign fraction_x__1 = fraction_x & {53{x_bexp__3 != 11'h000}}; assign fraction_y__1 = fraction_y & sign_ext_33643; assign xddend_x__2_squeezed_const_lsb_bits = 3'h0; assign result = narrowed_result ^ x_bexpor_mask__1; assign tuple_index_33653 = x[63:63]; assign wide_x_squeezed = {1'h0, fraction_x__1}; assign wide_y_shift_bits = {fraction_y__1, xddend_x__2_squeezed_const_lsb_bits}; assign shift = result + {10'h000, overflow_detected}; assign shrl_33661 = shift >= 11'h038 ? 56'h00_0000_0000_0000 : wide_y_shift_bits >> shift; assign shll_33663 = shift >= 11'h039 ? 57'h000_0000_0000_0000 : 57'h1ff_ffff_ffff_ffff << shift; assign xddend_x__2_squeezed = tuple_index_33653 ^ ~y_sign__2 ? -wide_x_squeezed : wide_x_squeezed; assign add_33674 = {{1{xddend_x__2_squeezed[53]}}, xddend_x__2_squeezed} + {2'h0, shrl_33661[55:3]}; assign sticky = ~({1'h0, ~y_fraction__3} | ~sign_ext_33643 | shll_33663[55:3]) != 53'h00_0000_0000_0000; assign concat_33680 = {add_33674[53:0], shrl_33661[2:1], shrl_33661[0] | sticky}; assign xbs_fraction__1 = add_33674[54] ? -concat_33680 : concat_33680; assign nor_33693 = ~(xbs_fraction__1[46] | xbs_fraction__1[45]); assign nor_33699 = ~(xbs_fraction__1[30] | xbs_fraction__1[29]); assign and_33724 = ~(xbs_fraction__1[48] | xbs_fraction__1[47]) & nor_33693; assign nor_33726 = ~(xbs_fraction__1[42] | xbs_fraction__1[41]); assign carry_bit = xbs_fraction__1[56]; assign and_33734 = ~(xbs_fraction__1[32] | xbs_fraction__1[31]) & nor_33699; assign nor_33736 = ~(xbs_fraction__1[26] | xbs_fraction__1[25]); assign and_33775 = ~(xbs_fraction__1[44] | xbs_fraction__1[43]) & nor_33726; assign nor_33776 = ~(xbs_fraction__1[44] | xbs_fraction__1[43] | nor_33726); assign nor_33778 = ~(xbs_fraction__1[54] | xbs_fraction__1[53]); assign and_33785 = ~(xbs_fraction__1[28] | xbs_fraction__1[27]) & nor_33736; assign nor_33786 = ~(xbs_fraction__1[28] | xbs_fraction__1[27] | nor_33736); assign nor_33788 = ~(xbs_fraction__1[38] | xbs_fraction__1[37]); assign nor_33762 = ~(xbs_fraction__1[24] | xbs_fraction__1[23]); assign nor_33763 = ~(xbs_fraction__1[22] | xbs_fraction__1[21]); assign nor_33768 = ~(xbs_fraction__1[18] | xbs_fraction__1[17]); assign nor_33769 = ~(xbs_fraction__1[20] | xbs_fraction__1[19]); assign nor_33758 = ~(xbs_fraction__1[14] | xbs_fraction__1[13]); assign nor_33759 = ~(xbs_fraction__1[16] | xbs_fraction__1[15]); assign nor_33749 = ~(xbs_fraction__1[6] | xbs_fraction__1[5]); assign nor_33750 = ~(xbs_fraction__1[8] | xbs_fraction__1[7]); assign nor_33819 = ~(xbs_fraction__1[50] | xbs_fraction__1[49]); assign nor_33820 = ~(~and_33724 | and_33775); assign and_33822 = ~(carry_bit | xbs_fraction__1[55]) & nor_33778; assign nor_33823 = ~(carry_bit | xbs_fraction__1[55] | nor_33778); assign nor_33830 = ~(xbs_fraction__1[34] | xbs_fraction__1[33]); assign nor_33831 = ~(~and_33734 | and_33785); assign and_33833 = ~(xbs_fraction__1[40] | xbs_fraction__1[39]) & nor_33788; assign nor_33834 = ~(xbs_fraction__1[40] | xbs_fraction__1[39] | nor_33788); assign and_33810 = nor_33762 & nor_33763; assign nor_33812 = ~(xbs_fraction__1[24] | ~xbs_fraction__1[23]); assign and_33815 = nor_33769 & nor_33768; assign nor_33816 = ~(xbs_fraction__1[20] | ~xbs_fraction__1[19]); assign and_33807 = nor_33759 & nor_33758; assign nor_33808 = ~(xbs_fraction__1[16] | ~xbs_fraction__1[15]); assign nor_33802 = ~(xbs_fraction__1[10] | xbs_fraction__1[9]); assign nor_33804 = ~(xbs_fraction__1[12] | xbs_fraction__1[11]); assign and_33798 = nor_33750 & nor_33749; assign nor_33799 = ~(xbs_fraction__1[8] | ~xbs_fraction__1[7]); assign nor_33793 = ~(xbs_fraction__1[2] | xbs_fraction__1[1]); assign nor_33795 = ~(xbs_fraction__1[4] | xbs_fraction__1[3]); assign and_33863 = ~(xbs_fraction__1[52] | xbs_fraction__1[51]) & nor_33819; assign and_33864 = and_33724 & and_33775; assign and_33866 = nor_33820 & ~nor_33776; assign and_33867 = nor_33820 & nor_33776; assign and_33875 = ~(xbs_fraction__1[36] | xbs_fraction__1[35]) & nor_33830; assign and_33876 = and_33734 & and_33785; assign and_33878 = nor_33831 & ~nor_33786; assign and_33879 = nor_33831 & nor_33786; assign and_33899 = and_33822 & and_33863; assign nor_33901 = ~(xbs_fraction__1[48] | xbs_fraction__1[47] | nor_33693); assign priority_sel_33909 = priority_sel_1b_2way({nor_33823, and_33822}, 1'h0, ~(xbs_fraction__1[54] | ~xbs_fraction__1[53]), ~(carry_bit | ~xbs_fraction__1[55])); assign and_33911 = and_33833 & and_33875; assign nor_33913 = ~(xbs_fraction__1[32] | xbs_fraction__1[31] | nor_33699); assign priority_sel_33921 = priority_sel_1b_2way({nor_33834, and_33833}, 1'h0, ~(xbs_fraction__1[38] | ~xbs_fraction__1[37]), ~(xbs_fraction__1[40] | ~xbs_fraction__1[39])); assign and_33896 = and_33810 & and_33815; assign priority_sel_33897 = priority_sel_2b_2way({~(xbs_fraction__1[24] | xbs_fraction__1[23] | nor_33763), and_33810}, {nor_33812, 1'h0}, {1'h1, ~(xbs_fraction__1[22] | ~xbs_fraction__1[21])}, {nor_33762, nor_33812}); assign and_33892 = nor_33804 & nor_33802; assign and_33888 = nor_33795 & nor_33793; assign concat_33944 = {1'h1, ~(xbs_fraction__1[52] | xbs_fraction__1[51] | nor_33819) ? {1'h1, ~(xbs_fraction__1[50] | ~xbs_fraction__1[49])} : {1'h0, ~(xbs_fraction__1[52] | ~xbs_fraction__1[51])}}; assign concat_33956 = {1'h1, ~(xbs_fraction__1[36] | xbs_fraction__1[35] | nor_33830) ? {1'h1, ~(xbs_fraction__1[34] | ~xbs_fraction__1[33])} : {1'h0, ~(xbs_fraction__1[36] | ~xbs_fraction__1[35])}}; assign concat_33932 = {1'h1, priority_sel_2b_2way({~(xbs_fraction__1[20] | xbs_fraction__1[19] | nor_33768), and_33815}, {nor_33816, 1'h0}, {1'h1, ~(xbs_fraction__1[18] | ~xbs_fraction__1[17])}, {nor_33769, nor_33816})}; assign concat_33929 = {and_33807, priority_sel_2b_2way({~(xbs_fraction__1[16] | xbs_fraction__1[15] | nor_33758), and_33807}, {nor_33808, 1'h0}, {1'h1, ~(xbs_fraction__1[14] | ~xbs_fraction__1[13])}, {nor_33759, nor_33808})}; assign concat_33928 = {1'h1, ~(xbs_fraction__1[12] | xbs_fraction__1[11] | nor_33802) ? {1'h1, ~(xbs_fraction__1[10] | ~xbs_fraction__1[9])} : {nor_33804, ~(xbs_fraction__1[12] | ~xbs_fraction__1[11])}}; assign concat_33926 = {and_33798, priority_sel_2b_2way({~(xbs_fraction__1[8] | xbs_fraction__1[7] | nor_33749), and_33798}, {nor_33799, 1'h0}, {1'h1, ~(xbs_fraction__1[6] | ~xbs_fraction__1[5])}, {nor_33750, nor_33799})}; assign concat_33925 = {1'h1, ~(xbs_fraction__1[4] | xbs_fraction__1[3] | nor_33793) ? {1'h1, ~(xbs_fraction__1[2] | ~xbs_fraction__1[1])} : {nor_33795, ~(xbs_fraction__1[4] | ~xbs_fraction__1[3])}}; assign and_33965 = and_33899 & and_33864; assign and_33971 = and_33911 & and_33876; assign and_33962 = and_33807 & and_33892; assign fraction_shift__3 = 3'h4; assign and_33992 = and_33965 & and_33971; assign priority_sel_33993 = priority_sel_4b_2way({~(~and_33899 | and_33864), and_33965}, 4'h0, {1'h1, nor_33820, and_33867 & ~and_33864 | nor_33901 & ~and_33866 & ~and_33867 & ~and_33864, priority_sel_1b_4way({nor_33901, and_33866, and_33867, and_33864}, 1'h0, ~(xbs_fraction__1[42] | ~xbs_fraction__1[41]), ~(xbs_fraction__1[44] | ~xbs_fraction__1[43]), ~(xbs_fraction__1[46] | ~xbs_fraction__1[45]), ~(xbs_fraction__1[48] | ~xbs_fraction__1[47]))}, {and_33899, priority_sel_3b_2way({~(~and_33822 | and_33863), and_33899}, {nor_33823, priority_sel_33909, 1'h0}, concat_33944, {1'h0, nor_33823, priority_sel_33909})}); assign priority_sel_33994 = priority_sel_4b_2way({~(~and_33911 | and_33876), and_33971}, 4'h0, {1'h1, nor_33831, and_33879 & ~and_33876 | nor_33913 & ~and_33878 & ~and_33879 & ~and_33876, priority_sel_1b_4way({nor_33913, and_33878, and_33879, and_33876}, 1'h0, ~(xbs_fraction__1[26] | ~xbs_fraction__1[25]), ~(xbs_fraction__1[28] | ~xbs_fraction__1[27]), ~(xbs_fraction__1[30] | ~xbs_fraction__1[29]), ~(xbs_fraction__1[32] | ~xbs_fraction__1[31]))}, {and_33911, priority_sel_3b_2way({~(~and_33833 | and_33875), and_33911}, {nor_33834, priority_sel_33921, 1'h0}, concat_33956, {1'h0, nor_33834, priority_sel_33921})}); assign sel_34109 = ~(~and_33896 | and_33962) ? {1'h1, ~(~and_33807 | and_33892) ? concat_33928 : concat_33929} : {and_33896, priority_sel_3b_2way({~(~and_33810 | and_33815), and_33896}, {priority_sel_33897, 1'h0}, concat_33932, {and_33810, priority_sel_33897})}; assign concat_33996 = {1'h1, and_33798 & and_33888 ? {fraction_shift__3, ~xbs_fraction__1[0]} : {1'h0, ~(~and_33798 | and_33888) ? concat_33925 : concat_33926}}; assign leading_zeroes = and_33965 & and_33992 ? {1'h1, and_33896 & and_33962 ? concat_33996 : {1'h0, sel_34109}} : {1'h0, priority_sel_5b_2way({~(~and_33965 | and_33971), and_33992}, {priority_sel_33993, 1'h0}, {1'h1, priority_sel_33994}, {and_33965, priority_sel_33993})}; assign cancel_fraction = leading_zeroes >= 6'h3a ? 58'h000_0000_0000_0000 : {1'h0, xbs_fraction__1} << leading_zeroes; assign cancel_fraction__1 = cancel_fraction[56:1]; assign carry_fraction__1 = {xbs_fraction__1[56:2], xbs_fraction__1[1] | xbs_fraction__1[0]}; assign shifted_fraction = carry_bit ? carry_fraction__1 : cancel_fraction__1; assign normal_chunk = shifted_fraction[2:0]; assign half_way_chunk = shifted_fraction[3:2]; assign do_round_up = normal_chunk > fraction_shift__3 | half_way_chunk == 2'h3; assign add_34024 = {1'h0, shifted_fraction[55:3]} + {53'h00_0000_0000_0000, do_round_up}; assign rounding_carry = add_34024[53]; assign add_34037 = {1'h0, x_bexp__3} + 12'h001; assign sub_34038 = {6'h00, rounding_carry} - {1'h0, leading_zeroes}; assign fraction_is_zero = add_33674 == 55'h00_0000_0000_0000 & ~(shrl_33661[1] | shrl_33661[2]) & ~(shrl_33661[0] | sticky); assign wide_exponent_associative_element = {1'h0, add_34037}; assign wide_exponent_associative_element__1 = {{6{sub_34038[6]}}, sub_34038}; assign wide_exponent = wide_exponent_associative_element + wide_exponent_associative_element__1; assign wide_exponent__1 = wide_exponent & {13{~fraction_is_zero}}; assign MAX_EXPONENT = 11'h7ff; assign wide_exponent__2 = wide_exponent__1[11:0] & {12{~wide_exponent__1[12]}}; assign eq_34053 = x_bexp__3 == MAX_EXPONENT; assign eq_34054 = x_fraction__1 == 52'h0_0000_0000_0000; assign eq_34055 = y_bexp__3 == MAX_EXPONENT; assign eq_34056 = y_fraction__3 == 52'h0_0000_0000_0000; assign x_sign__1 = overflow_detected ? tuple_index_33653 : ~y_sign__2; assign y_sign__3 = overflow_detected ? ~y_sign__2 : tuple_index_33653; assign fraction_shift__2 = 3'h3; assign is_operand_inf = eq_34053 & eq_34054 | eq_34055 & eq_34056; assign and_reduce_34076 = &wide_exponent__2[10:0]; assign has_pos_inf = ~(~eq_34053 | ~eq_34054 | x_sign__1) | ~(~eq_34055 | ~eq_34056 | y_sign__3); assign has_neg_inf = eq_34053 & eq_34054 & x_sign__1 | eq_34055 & eq_34056 & y_sign__3; assign rounded_fraction = {add_34024, normal_chunk}; assign fraction_shift__1 = rounding_carry ? fraction_shift__3 : fraction_shift__2; assign shrl_34090 = rounded_fraction >> fraction_shift__1; assign is_result_nan = ~(~eq_34053 | eq_34054) | ~(~eq_34055 | eq_34056) | has_pos_inf & has_neg_inf; assign result_sign = priority_sel_1b_2way({add_33674[54], fraction_is_zero}, ~(~tuple_index_33653 | y_sign__2), ~y_sign__3, y_sign__3); assign result_fraction = shrl_34090[51:0]; assign sign_ext_34096 = {52{~(is_operand_inf | wide_exponent__2[11] | and_reduce_34076 | ~((|wide_exponent__2[11:1]) | wide_exponent__2[0]))}}; assign result_sign__1 = is_operand_inf ? ~has_pos_inf : result_sign; assign result_fraction__3 = result_fraction & sign_ext_34096; assign FRACTION_HIGH_BIT = 52'h8_0000_0000_0000; assign result_sign__2 = ~is_result_nan & result_sign__1; assign result_exponent__2 = is_result_nan | is_operand_inf | wide_exponent__2[11] | and_reduce_34076 ? MAX_EXPONENT : wide_exponent__2[10:0]; assign result_fraction__4 = is_result_nan ? FRACTION_HIGH_BIT : result_fraction__3; assign out = {result_sign__2, result_exponent__2, result_fraction__4}; endmodule