module __hfloat16__to_uint16(
  input wire [15:0] x,
  output wire [15:0] out
);
  wire [4:0] x_bexp__2;
  wire [4:0] exp;
  wire [3:0] bit_slice_447;
  wire [4:0] add_450;
  wire [5:0] concat_452;
  wire [9:0] x_fraction__2;
  wire [5:0] neg_456;
  wire [15:0] fraction;
  wire [31:0] effective_exp;
  wire [10:0] fraction_shift_bits;
  wire eq_464;
  wire ne_465;
  wire x_sign__2;
  wire [15:0] and_488;
  wire [15:0] result;
  assign x_bexp__2 = x[14:10];
  assign exp = x_bexp__2 + 5'h11;
  assign bit_slice_447 = exp[4:1];
  assign add_450 = {{1{bit_slice_447[3]}}, bit_slice_447} + 5'h1b;
  assign concat_452 = {add_450, exp[0]};
  assign x_fraction__2 = x[9:0];
  assign neg_456 = -concat_452;
  assign fraction = {6'h01, x_fraction__2};
  assign effective_exp = {{26{concat_452[5]}}, concat_452};
  assign fraction_shift_bits = {1'h1, x_fraction__2};
  assign eq_464 = x_bexp__2 == 5'h1f;
  assign ne_465 = x_fraction__2 != 10'h000;
  assign x_sign__2 = x[15:15];
  assign and_488 = (x_bexp__2 == 5'h0f ? 16'h0001 : (effective_exp[31] ? {5'h00, {{26{neg_456[5]}}, neg_456} >= 32'h0000_000b ? 11'h000 : fraction_shift_bits >> {{26{neg_456[5]}}, neg_456}} : ($signed(concat_452) > $signed(6'h00) ? (effective_exp >= 32'h0000_0010 ? 16'h0000 : fraction << effective_exp) : fraction))) & {16{~(eq_464 & ne_465 | exp[4])}};
  assign result = ~(~eq_464 | ne_465) | x_sign__2 ? {16{~x_sign__2}} : and_488;
  assign out = result;
endmodule