module __float32__mul(
  input wire [31:0] x,
  input wire [31:0] y,
  output wire [31:0] out
);
  // lint_off MULTIPLY
  function automatic [47:0] umul48b_24b_x_24b (input reg [23:0] lhs, input reg [23:0] rhs);
    begin
      umul48b_24b_x_24b = lhs * rhs;
    end
  endfunction
  // lint_on MULTIPLY
  wire [7:0] x_bexp__1;
  wire [7:0] y_bexp__2;
  wire [22:0] x_fraction__1;
  wire [22:0] y_fraction__1;
  wire eq_627;
  wire eq_628;
  wire [23:0] x_fraction__3;
  wire [23:0] y_fraction__3;
  wire nor_632;
  wire [47:0] umul_635;
  wire [8:0] add_637;
  wire [47:0] fraction;
  wire [9:0] exp;
  wire [47:0] fraction__1;
  wire [9:0] exp__1;
  wire [9:0] exp__2;
  wire fraction__8;
  wire [47:0] fraction__2;
  wire [47:0] fraction__3;
  wire or_662;
  wire greater_than_half_way;
  wire [22:0] fraction__5;
  wire do_round_up;
  wire [23:0] fraction__6;
  wire [23:0] fraction__7;
  wire [9:0] add_676;
  wire [9:0] exp__3;
  wire is_subnormal;
  wire [7:0] high_exp;
  wire [8:0] result_exp;
  wire eq_683;
  wire eq_684;
  wire eq_685;
  wire eq_686;
  wire [8:0] result_exp__1;
  wire has_inf_arg;
  wire and_reduce_693;
  wire has_0_arg;
  wire is_result_nan;
  wire x_sign__1;
  wire y_sign__1;
  wire [22:0] result_fraction;
  wire result_sign;
  wire [22:0] result_fraction__3;
  wire [22:0] nan_fraction;
  wire result_sign__1;
  wire [7:0] result_exp__4;
  wire [22:0] result_fraction__4;
  assign x_bexp__1 = x[30:23];
  assign y_bexp__2 = y[30:23];
  assign x_fraction__1 = x[22:0];
  assign y_fraction__1 = y[22:0];
  assign eq_627 = x_bexp__1 == 8'h00;
  assign eq_628 = y_bexp__2 == 8'h00;
  assign x_fraction__3 = {1'h1, x_fraction__1};
  assign y_fraction__3 = {1'h1, y_fraction__1};
  assign nor_632 = ~(eq_627 | eq_628);
  assign umul_635 = umul48b_24b_x_24b(x_fraction__3, y_fraction__3);
  assign add_637 = {1'h0, x_bexp__1} + {1'h0, y_bexp__2};
  assign fraction = umul_635 & {48{nor_632}};
  assign exp = {1'h0, add_637} + 10'h381;
  assign fraction__1 = fraction >> fraction[47];
  assign exp__1 = exp & {10{nor_632}};
  assign exp__2 = exp__1 + {9'h000, fraction[47]};
  assign fraction__8 = fraction__1[0] | fraction[0];
  assign fraction__2 = {fraction__1[47:1], fraction__8};
  assign fraction__3 = $signed(exp__2) <= $signed(10'h000) ? {1'h0, fraction__1[47:1]} : fraction__2;
  assign or_662 = fraction__3[21:1] != 21'h00_0000 | fraction__3[0] | fraction__1[0] | fraction[0];
  assign greater_than_half_way = fraction__3[22] & or_662;
  assign fraction__5 = fraction__3[45:23];
  assign do_round_up = greater_than_half_way | fraction__3[22] & ~or_662 & fraction__3[23];
  assign fraction__6 = {1'h0, fraction__5};
  assign fraction__7 = fraction__6 + {23'h00_0000, do_round_up};
  assign add_676 = exp__2 + 10'h001;
  assign exp__3 = fraction__7[23] ? add_676 : exp__2;
  assign is_subnormal = $signed(exp__3) <= $signed(10'h000);
  assign high_exp = 8'hff;
  assign result_exp = exp__3[8:0];
  assign eq_683 = x_bexp__1 == high_exp;
  assign eq_684 = x_fraction__1 == 23'h00_0000;
  assign eq_685 = y_bexp__2 == high_exp;
  assign eq_686 = y_fraction__1 == 23'h00_0000;
  assign result_exp__1 = result_exp & {9{~is_subnormal}};
  assign has_inf_arg = eq_683 & eq_684 | eq_685 & eq_686;
  assign and_reduce_693 = &result_exp__1[7:0];
  assign has_0_arg = eq_627 | eq_628;
  assign is_result_nan = ~(~eq_683 | eq_684) | ~(~eq_685 | eq_686) | has_0_arg & has_inf_arg;
  assign x_sign__1 = x[31:31];
  assign y_sign__1 = y[31:31];
  assign result_fraction = fraction__7[22:0];
  assign result_sign = x_sign__1 ^ y_sign__1;
  assign result_fraction__3 = result_fraction & {23{~(has_inf_arg | result_exp__1[8] | and_reduce_693 | is_subnormal)}};
  assign nan_fraction = 23'h40_0000;
  assign result_sign__1 = ~is_result_nan & result_sign;
  assign result_exp__4 = is_result_nan | has_inf_arg | result_exp__1[8] | and_reduce_693 ? high_exp : result_exp__1[7:0];
  assign result_fraction__4 = is_result_nan ? nan_fraction : result_fraction__3;
  assign out = {result_sign__1, result_exp__4, result_fraction__4};
endmodule