module __float32__lt_2(
  input wire [31:0] x,
  input wire [31:0] y,
  output wire out
);
  function automatic priority_sel_1b_3way (input reg [2:0] sel, input reg case0, input reg case1, input reg case2, input reg default_value);
    begin
      casez (sel)
        3'b??1: begin
          priority_sel_1b_3way = case0;
        end
        3'b?10: begin
          priority_sel_1b_3way = case1;
        end
        3'b100: begin
          priority_sel_1b_3way = case2;
        end
        3'b000: begin
          priority_sel_1b_3way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_1b_3way = 1'dx;
        end
      endcase
    end
  endfunction
  wire [7:0] x_bexp__1;
  wire [7:0] y_bexp__2;
  wire eq_691;
  wire eq_692;
  wire [22:0] x_fraction__1;
  wire [22:0] y_fraction__1;
  wire x_sign__2;
  wire y_sign__1;
  wire [22:0] x__1_fraction__2;
  wire [22:0] y__1_fraction__2;
  wire eq_709;
  wire eq_exp;
  wire gt_fraction;
  wire and_713;
  wire and_714;
  wire and_716;
  wire gt_exp;
  wire nor_719;
  wire abs_gt;
  wire and_735;
  wire result;
  wire and_738;
  assign x_bexp__1 = x[30:23];
  assign y_bexp__2 = y[30:23];
  assign eq_691 = x_bexp__1 == 8'h00;
  assign eq_692 = y_bexp__2 == 8'h00;
  assign x_fraction__1 = x[22:0];
  assign y_fraction__1 = y[22:0];
  assign x_sign__2 = x[31:31];
  assign y_sign__1 = y[31:31];
  assign x__1_fraction__2 = x_fraction__1 & {23{~eq_691}};
  assign y__1_fraction__2 = y_fraction__1 & {23{~eq_692}};
  assign eq_709 = x_sign__2 == y_sign__1;
  assign eq_exp = x_bexp__1 == y_bexp__2;
  assign gt_fraction = x__1_fraction__2 > y__1_fraction__2;
  assign and_713 = x_bexp__1 == 8'hff & x_fraction__1 != 23'h00_0000;
  assign and_714 = y_bexp__2 == 8'hff & y_fraction__1 != 23'h00_0000;
  assign and_716 = eq_691 & eq_692;
  assign gt_exp = x_bexp__1 > y_bexp__2;
  assign nor_719 = ~(and_713 | and_714);
  assign abs_gt = gt_exp | eq_exp & gt_fraction;
  assign and_735 = ~abs_gt & ~(nor_719 & (eq_709 & eq_exp & x__1_fraction__2 == y__1_fraction__2 | and_716));
  assign result = priority_sel_1b_3way({~(~x_sign__2 | y_sign__1), ~(x_sign__2 | ~y_sign__1), ~(x_sign__2 | y_sign__1)}, abs_gt, 1'h1, 1'h0, and_735);
  assign and_738 = nor_719 & (eq_709 & eq_exp & x_fraction__1 == y_fraction__1 | and_716);
  assign out = ~(and_713 | and_714 | (~and_738 & ~(and_713 | and_714 | ~result) | and_738));
endmodule