module __bfloat16__ldexp(
  input wire [15:0] f,
  input wire [31:0] e,
  output wire [15:0] out
);
  wire [7:0] f_bexp__1;
  wire eq_453;
  wire [7:0] add_454;
  wire [6:0] tuple_index_458;
  wire [32:0] e__1;
  wire [6:0] f__1_fraction;
  wire [32:0] MAX_EXPONENT;
  wire [7:0] BIAS;
  wire [32:0] MIN_EXPONENT;
  wire sgt_470;
  wire [7:0] add_471;
  wire slt_475;
  wire [7:0] result__2_bexp__1;
  wire eq_480;
  wire eq_481;
  wire f_sign;
  wire nor_489;
  wire [6:0] and_492;
  wire [15:0] result__5;
  assign f_bexp__1 = f[14:7];
  assign eq_453 = f_bexp__1 == 8'h00;
  assign add_454 = f_bexp__1 + 8'h81;
  assign tuple_index_458 = f[6:0];
  assign e__1 = {{1{e[31]}}, e} + {{25{add_454[7]}}, add_454};
  assign f__1_fraction = tuple_index_458 & {7{~eq_453}};
  assign MAX_EXPONENT = 33'h0_0000_007f;
  assign BIAS = 8'h7f;
  assign MIN_EXPONENT = 33'h1_ffff_ff82;
  assign sgt_470 = $signed(e__1) > $signed(MAX_EXPONENT);
  assign add_471 = e__1[7:0] + BIAS;
  assign slt_475 = $signed(e__1) < $signed(MIN_EXPONENT);
  assign result__2_bexp__1 = slt_475 ? {7'h00, e__1 == 33'h1_ffff_ff81 & f__1_fraction == 7'h7f} : (sgt_470 ? 8'hff : add_471);
  assign eq_480 = f_bexp__1 == 8'hff;
  assign eq_481 = f__1_fraction == 7'h00;
  assign f_sign = f[15:15];
  assign nor_489 = ~(~eq_480 | eq_481);
  assign and_492 = tuple_index_458 & {7{~(result__2_bexp__1 == 8'h00 | slt_475 | sgt_470 | eq_453)}};
  assign result__5 = {~(nor_489 | ~f_sign), nor_489 ? 8'hff : (eq_453 | eq_480 & eq_481 ? f_bexp__1 : result__2_bexp__1), nor_489 ? 7'h40 : and_492};
  assign out = result__5;
endmodule