module __float32__from_int32(
  input wire [31:0] x,
  output wire [31:0] out
);
  wire sign;
  wire [30:0] fraction;
  wire [30:0] reverse_401;
  wire [31:0] one_hot_402;
  wire [4:0] encode_404;
  wire [5:0] add_409;
  wire [32:0] fraction__1_narrowed;
  wire fraction__5;
  wire [2:0] normal_chunk;
  wire [1:0] half_way_chunk;
  wire [23:0] add_428;
  wire [1:0] bexp_associative_element_squeezed;
  wire [7:0] lz;
  wire [7:0] bexp__1;
  wire [22:0] fraction__4;
  wire and_reduce_442;
  wire ne_443;
  wire is_neg_int_max;
  wire or_446;
  wire [22:0] and_457;
  assign sign = x[31];
  assign fraction = sign ? -x[30:0] : x[30:0];
  assign reverse_401 = {fraction[0], fraction[1], fraction[2], fraction[3], fraction[4], fraction[5], fraction[6], fraction[7], fraction[8], fraction[9], fraction[10], fraction[11], fraction[12], fraction[13], fraction[14], fraction[15], fraction[16], fraction[17], fraction[18], fraction[19], fraction[20], fraction[21], fraction[22], fraction[23], fraction[24], fraction[25], fraction[26], fraction[27], fraction[28], fraction[29], fraction[30]};
  assign one_hot_402 = {reverse_401[30:0] == 31'h0000_0000, reverse_401[30] && reverse_401[29:0] == 30'h0000_0000, reverse_401[29] && reverse_401[28:0] == 29'h0000_0000, reverse_401[28] && reverse_401[27:0] == 28'h000_0000, reverse_401[27] && reverse_401[26:0] == 27'h000_0000, reverse_401[26] && reverse_401[25:0] == 26'h000_0000, reverse_401[25] && reverse_401[24:0] == 25'h000_0000, reverse_401[24] && reverse_401[23:0] == 24'h00_0000, reverse_401[23] && reverse_401[22:0] == 23'h00_0000, reverse_401[22] && reverse_401[21:0] == 22'h00_0000, reverse_401[21] && reverse_401[20:0] == 21'h00_0000, reverse_401[20] && reverse_401[19:0] == 20'h0_0000, reverse_401[19] && reverse_401[18:0] == 19'h0_0000, reverse_401[18] && reverse_401[17:0] == 18'h0_0000, reverse_401[17] && reverse_401[16:0] == 17'h0_0000, reverse_401[16] && reverse_401[15:0] == 16'h0000, reverse_401[15] && reverse_401[14:0] == 15'h0000, reverse_401[14] && reverse_401[13:0] == 14'h0000, reverse_401[13] && reverse_401[12:0] == 13'h0000, reverse_401[12] && reverse_401[11:0] == 12'h000, reverse_401[11] && reverse_401[10:0] == 11'h000, reverse_401[10] && reverse_401[9:0] == 10'h000, reverse_401[9] && reverse_401[8:0] == 9'h000, reverse_401[8] && reverse_401[7:0] == 8'h00, reverse_401[7] && reverse_401[6:0] == 7'h00, reverse_401[6] && reverse_401[5:0] == 6'h00, reverse_401[5] && reverse_401[4:0] == 5'h00, reverse_401[4] && reverse_401[3:0] == 4'h0, reverse_401[3] && reverse_401[2:0] == 3'h0, reverse_401[2] && reverse_401[1:0] == 2'h0, reverse_401[1] && !reverse_401[0], reverse_401[0]};
  assign encode_404 = {one_hot_402[16] | one_hot_402[17] | one_hot_402[18] | one_hot_402[19] | one_hot_402[20] | one_hot_402[21] | one_hot_402[22] | one_hot_402[23] | one_hot_402[24] | one_hot_402[25] | one_hot_402[26] | one_hot_402[27] | one_hot_402[28] | one_hot_402[29] | one_hot_402[30] | one_hot_402[31], one_hot_402[8] | one_hot_402[9] | one_hot_402[10] | one_hot_402[11] | one_hot_402[12] | one_hot_402[13] | one_hot_402[14] | one_hot_402[15] | one_hot_402[24] | one_hot_402[25] | one_hot_402[26] | one_hot_402[27] | one_hot_402[28] | one_hot_402[29] | one_hot_402[30] | one_hot_402[31], one_hot_402[4] | one_hot_402[5] | one_hot_402[6] | one_hot_402[7] | one_hot_402[12] | one_hot_402[13] | one_hot_402[14] | one_hot_402[15] | one_hot_402[20] | one_hot_402[21] | one_hot_402[22] | one_hot_402[23] | one_hot_402[28] | one_hot_402[29] | one_hot_402[30] | one_hot_402[31], one_hot_402[2] | one_hot_402[3] | one_hot_402[6] | one_hot_402[7] | one_hot_402[10] | one_hot_402[11] | one_hot_402[14] | one_hot_402[15] | one_hot_402[18] | one_hot_402[19] | one_hot_402[22] | one_hot_402[23] | one_hot_402[26] | one_hot_402[27] | one_hot_402[30] | one_hot_402[31], one_hot_402[1] | one_hot_402[3] | one_hot_402[5] | one_hot_402[7] | one_hot_402[9] | one_hot_402[11] | one_hot_402[13] | one_hot_402[15] | one_hot_402[17] | one_hot_402[19] | one_hot_402[21] | one_hot_402[23] | one_hot_402[25] | one_hot_402[27] | one_hot_402[29] | one_hot_402[31]};
  assign add_409 = {1'h0, encode_404} + 6'h03;
  assign fraction__1_narrowed = add_409 >= 6'h21 ? 33'h0_0000_0000 : {2'h0, fraction} << add_409;
  assign fraction__5 = fraction__1_narrowed[7] | fraction__1_narrowed[6:3] != 4'h0;
  assign normal_chunk = {fraction__1_narrowed[9:8], fraction__5};
  assign half_way_chunk = fraction__1_narrowed[10:9];
  assign add_428 = {1'h0, fraction__1_narrowed[32:10]} + {23'h00_0000, normal_chunk > 3'h4 | half_way_chunk == 2'h3};
  assign bexp_associative_element_squeezed = 2'h1;
  assign lz = {3'h0, encode_404};
  assign bexp__1 = {6'h27, add_428[23] ? 2'h2 : bexp_associative_element_squeezed} - lz;
  assign fraction__4 = add_428[22:0];
  assign and_reduce_442 = &bexp__1[6:0];
  assign ne_443 = fraction__4 != 23'h00_0000;
  assign is_neg_int_max = x == 32'h8000_0000;
  assign or_446 = bexp__1[7] | and_reduce_442 | ne_443;
  assign and_457 = fraction__4 & {23{~(is_neg_int_max | ~(bexp__1[7] | and_reduce_442 | ne_443))}};
  assign out = {is_neg_int_max | ~is_neg_int_max & or_446 & sign, is_neg_int_max ? 8'h9e : bexp__1 & {8{or_446}}, and_457};
endmodule