Action `3ea7f9c3648fb1a27a9b963a9af87416ce6e7bf0270e1f8231df8c83a4356281`

Summary

state: not queued

kind: combo_verilog_to_yosys_abc_aig

subject: verilog=ae7fe81cbe37 top=__float32__fast_rsqrt

crate:v0.11.0dso:-driver:-

Upstream Dependencies

Role	Action ID	State	Kind	Subject	Output
`verilog_action_id`	`ae7fe81cbe376de01d05941696c431dcd9a86fecad92efe9cf10e93e33a13dfc`	done	`ir_fn_to_combinational_verilog`	ir=6479a51a8589 top=__float32__fast_rsqrt system_verilog=false	`verilog_file payload/result.v`

Failure

timeout at 2026-02-20T04:51:51.204654958+00:00 by unknown-host:2098204:web-runner-2

summary: TIMEOUT(300) docker run exceeded 300 seconds (container=xlsynth-bvc-run-3ea7f9c3648fb1a2-2098204-81)

TIMEOUT(300) docker run exceeded 300 seconds (container=xlsynth-bvc-run-3ea7f9c3648fb1a2-2098204-81)
command:
docker run --name xlsynth-bvc-run-3ea7f9c3648fb1a2-2098204-81 --rm --pull never --network none -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/artifacts/ae/7f/ae7fe81cbe376de01d05941696c431dcd9a86fecad92efe9cf10e93e33a13dfc/payload/result.v:/inputs/input.v:ro -v /home/cdleary/proj/xlsynth-bvc/flows/yosys_to_aig.ys:/inputs/flow.ys:ro -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/.staging/3ea7f9c3648fb1a27a9b963a9af87416ce6e7bf0270e1f8231df8c83a4356281-2098204-1771562810868698671/payload:/outputs -e READ_VERILOG_FLAGS= -e VERILOG_TOP_MODULE_NAME=__float32__fast_rsqrt xlsynth-bvc-yosys-abc:ubuntu24.04 bash -lc
set -euo pipefail
{
echo "read_verilog ${READ_VERILOG_FLAGS} /inputs/input.v"
if [ -n "${VERILOG_TOP_MODULE_NAME:-}" ]; then
echo "hierarchy -check -top ${VERILOG_TOP_MODULE_NAME}"
fi
echo "script /inputs/flow.ys"
echo "write_aiger /outputs/result.aig"
} > /tmp/run.ys
yosys -s /tmp/run.ys
test -s /outputs/result.aig

cleanup: removed timed-out container
stdout:

/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/

Yosys 0.33 (git sha1 2584903a060)

-- Executing script file `/tmp/run.ys' --

1. Executing Verilog-2005 frontend: /inputs/input.v
Parsing Verilog input from `/inputs/input.v' to AST representation.
Generating RTLIL representation for module `\__float32__fast_rsqrt'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module: \__float32__fast_rsqrt

2.2. Analyzing design hierarchy..
Top module: \__float32__fast_rsqrt
Removed 0 unused modules.

-- Executing script file `/inputs/flow.ys' --

3. Executing PROC pass (convert processes to netlists).

3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed 1 dead cases from process $proc$/inputs/input.v:0$529 in module __float32__fast_rsqrt.
Marked 1 switch rules as full_case in process $proc$/inputs/input.v:0$529 in module __float32__fast_rsqrt.
Removed 1 dead cases from process $proc$/inputs/input.v:0$512 in module __float32__fast_rsqrt.
Marked 1 switch rules as full_case in process $proc$/inputs/input.v:0$512 in module __float32__fast_rsqrt.
Removed 1 dead cases from process $proc$/inputs/input.v:0$498 in module __float32__fast_rsqrt.
Marked 1 switch rules as full_case in process $proc$/inputs/input.v:0$498 in module __float32__fast_rsqrt.
Removed 1 dead cases from process $proc$/inputs/input.v:0$484 in module __float32__fast_rsqrt.
Marked 1 switch rules as full_case in process $proc$/inputs/input.v:0$484 in module __float32__fast_rsqrt.
Removed 1 dead cases from process $proc$/inputs/input.v:0$470 in module __float32__fast_rsqrt.
Marked 1 switch rules as full_case in process $proc$/inputs/input.v:0$470 in module __float32__fast_rsqrt.
Removed 1 dead cases from process $proc$/inputs/input.v:0$456 in module __float32__fast_rsqrt.
Marked 1 switch rules as full_case in process $proc$/inputs/input.v:0$456 in module __float32__fast_rsqrt.
Removed 1 dead cases from process $proc$/inputs/input.v:0$442 in module __float32__fast_rsqrt.
Marked 1 switch rules as full_case in process $proc$/inputs/input.v:0$442 in module __float32__fast_rsqrt.
Removed a total of 7 dead cases.

3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 54 assignments to connections.

3.4. Executing PROC_INIT pass (extract init attributes).

3.5. Executing PROC_ARST pass (detect async resets in processes).

3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~7 debug messages>

3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$529'.
1/1: $1\priority_sel_1b_2way$func$/inputs/input.v:597$20.$result[0:0]$537
Creating decoders for process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$523'.
Creating decoders for process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$512'.
1/1: $1\priority_sel_3b_2way$func$/inputs/input.v:524$18.$result[2:0]$522
Creating decoders for process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$498'.
1/1: $1\priority_sel_2b_2way$func$/inputs/input.v:523$17.$result[1:0]$511
Creating decoders for process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$484'.
1/1: $1\priority_sel_2b_2way$func$/inputs/input.v:520$16.$result[1:0]$497
Creating decoders for process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$470'.
1/1: $1\priority_sel_2b_2way$func$/inputs/input.v:518$15.$result[1:0]$483
Creating decoders for process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$456'.
1/1: $1\priority_sel_2b_2way$func$/inputs/input.v:517$14.$result[1:0]$469
Creating decoders for process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$442'.
1/1: $1\priority_sel_2b_2way$func$/inputs/input.v:512$13.$result[1:0]$455
Creating decoders for process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$436'.
Creating decoders for process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$430'.

3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_1b_2way$func$/inputs/input.v:597$10.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$529'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_1b_2way$func$/inputs/input.v:597$20.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$529'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_1b_2way$func$/inputs/input.v:597$20.sel' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$529'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_1b_2way$func$/inputs/input.v:597$20.case0' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$529'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_1b_2way$func$/inputs/input.v:597$20.case1' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$529'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_1b_2way$func$/inputs/input.v:597$20.default_value' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$529'.
No latch inferred for signal `\__float32__fast_rsqrt.\umul48b_24b_x_24b$func$/inputs/input.v:568$9.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$523'.
No latch inferred for signal `\__float32__fast_rsqrt.\umul48b_24b_x_24b$func$/inputs/input.v:568$19.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$523'.
No latch inferred for signal `\__float32__fast_rsqrt.\umul48b_24b_x_24b$func$/inputs/input.v:568$19.lhs' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$523'.
No latch inferred for signal `\__float32__fast_rsqrt.\umul48b_24b_x_24b$func$/inputs/input.v:568$19.rhs' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$523'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_3b_2way$func$/inputs/input.v:524$8.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$512'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_3b_2way$func$/inputs/input.v:524$18.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$512'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_3b_2way$func$/inputs/input.v:524$18.sel' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$512'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_3b_2way$func$/inputs/input.v:524$18.case0' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$512'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_3b_2way$func$/inputs/input.v:524$18.case1' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$512'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_3b_2way$func$/inputs/input.v:524$18.default_value' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$512'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:523$7.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$498'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:523$17.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$498'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:523$17.sel' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$498'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:523$17.case0' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$498'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:523$17.case1' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$498'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:523$17.default_value' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$498'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:520$6.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$484'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:520$16.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$484'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:520$16.sel' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$484'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:520$16.case0' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$484'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:520$16.case1' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$484'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:520$16.default_value' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$484'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:518$5.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$470'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:518$15.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$470'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:518$15.sel' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$470'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:518$15.case0' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$470'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:518$15.case1' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$470'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:518$15.default_value' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$470'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:517$4.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$456'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:517$14.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$456'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:517$14.sel' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$456'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:517$14.case0' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$456'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:517$14.case1' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$456'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:517$14.default_value' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$456'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:512$3.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$442'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:512$13.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$442'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:512$13.sel' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$442'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:512$13.case0' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$442'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:512$13.case1' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$442'.
No latch inferred for signal `\__float32__fast_rsqrt.\priority_sel_2b_2way$func$/inputs/input.v:512$13.default_value' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$442'.
No latch inferred for signal `\__float32__fast_rsqrt.\umul48b_24b_x_24b$func$/inputs/input.v:422$2.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$436'.
No latch inferred for signal `\__float32__fast_rsqrt.\umul48b_24b_x_24b$func$/inputs/input.v:422$12.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$436'.
No latch inferred for signal `\__float32__fast_rsqrt.\umul48b_24b_x_24b$func$/inputs/input.v:422$12.lhs' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$436'.
No latch inferred for signal `\__float32__fast_rsqrt.\umul48b_24b_x_24b$func$/inputs/input.v:422$12.rhs' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$436'.
No latch inferred for signal `\__float32__fast_rsqrt.\umul48b_24b_x_24b$func$/inputs/input.v:376$1.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$430'.
No latch inferred for signal `\__float32__fast_rsqrt.\umul48b_24b_x_24b$func$/inputs/input.v:376$11.$result' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$430'.
No latch inferred for signal `\__float32__fast_rsqrt.\umul48b_24b_x_24b$func$/inputs/input.v:376$11.lhs' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$430'.
No latch inferred for signal `\__float32__fast_rsqrt.\umul48b_24b_x_24b$func$/inputs/input.v:376$11.rhs' from process `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$430'.

3.9. Executing PROC_DFF pass (convert process syncs to FFs).

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$529'.
Removing empty process `__float32__fast_rsqrt.$proc$/inputs/input.v:0$529'.
Removing empty process `__float32__fast_rsqrt.$proc$/inputs/input.v:0$523'.
Found and cleaned up 1 empty switch in `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$512'.
Removing empty process `__float32__fast_rsqrt.$proc$/inputs/input.v:0$512'.
Found and cleaned up 1 empty switch in `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$498'.
Removing empty process `__float32__fast_rsqrt.$proc$/inputs/input.v:0$498'.
Found and cleaned up 1 empty switch in `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$484'.
Removing empty process `__float32__fast_rsqrt.$proc$/inputs/input.v:0$484'.
Found and cleaned up 1 empty switch in `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$470'.
Removing empty process `__float32__fast_rsqrt.$proc$/inputs/input.v:0$470'.
Found and cleaned up 1 empty switch in `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$456'.
Removing empty process `__float32__fast_rsqrt.$proc$/inputs/input.v:0$456'.
Found and cleaned up 1 empty switch in `\__float32__fast_rsqrt.$proc$/inputs/input.v:0$442'.
Removing empty process `__float32__fast_rsqrt.$proc$/inputs/input.v:0$442'.
Removing empty process `__float32__fast_rsqrt.$proc$/inputs/input.v:0$436'.
Removing empty process `__float32__fast_rsqrt.$proc$/inputs/input.v:0$430'.
Cleaned up 7 empty switches.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float32__fast_rsqrt.
<suppressed ~33 debug messages>

4. Executing OPT pass (performing simple optimizations).

4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float32__fast_rsqrt.

4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__float32__fast_rsqrt'.
<suppressed ~66 debug messages>
Removed a total of 22 cells.

4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \__float32__fast_rsqrt..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Replacing known input bits on port B of cell $ternary$/inputs/input.v:530$278: \carry_fraction__1 -> { 1'1 \carry_fraction__1 [25:0] }
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~32 debug messages>

4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \__float32__fast_rsqrt.
Performed a total of 0 changes.

4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__float32__fast_rsqrt'.
Removed a total of 0 cells.

4.6. Executing OPT_DFF pass (perform DFF optimizations).

4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \__float32__fast_rsqrt..
Removed 5 unused cells and 318 unused wires.
<suppressed ~6 debug messages>

4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float32__fast_rsqrt.

4.9. Rerunning OPT passes. (Maybe there is more to do..)

4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \__float32__fast_rsqrt..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~32 debug messages>

4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \__float32__fast_rsqrt.
Performed a total of 0 changes.

4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__float32__fast_rsqrt'.
Removed a total of 0 cells.

4.13. Executing OPT_DFF pass (perform DFF optimizations).

4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \__float32__fast_rsqrt..

4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float32__fast_rsqrt.

4.16. Finished OPT passes. (There is nothing left to do.)

5. Executing TECHMAP pass (map to technology primitives).

5.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

5.2. Continuing TECHMAP pass.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=10:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=10:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=10:B_SIGNED=0:B_WIDTH=10:Y_WIDTH=10:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$le:A_SIGNED=1:A_WIDTH=10:B_SIGNED=1:B_WIDTH=10:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$le:A_SIGNED=1:A_WIDTH=10:B_SIGNED=1:B_WIDTH=10:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$le:A_SIGNED=1:A_WIDTH=10:B_SIGNED=1:B_WIDTH=10:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $and.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=24:B_SIGNED=0:B_WIDTH=24:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=24:B_SIGNED=0:B_WIDTH=24:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=24:B_SIGNED=0:B_WIDTH=24:Y_WIDTH=24:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$le:A_SIGNED=1:A_WIDTH=9:B_SIGNED=1:B_WIDTH=9:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$le:A_SIGNED=1:A_WIDTH=9:B_SIGNED=1:B_WIDTH=9:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$le:A_SIGNED=1:A_WIDTH=9:B_SIGNED=1:B_WIDTH=9:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_and.
Running "alumacc" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=27:B_SIGNED=0:B_WIDTH=27:Y_WIDTH=27:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=27:B_SIGNED=0:B_WIDTH=27:Y_WIDTH=27:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=27:B_SIGNED=0:B_WIDTH=27:Y_WIDTH=27:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $logic_not.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=9:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=9:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=9:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$constmap:a1beb42ad934f6518d0995b1acc6baa703133790$paramod$bf6361c041fa77978c749d132b4933eb96252d98\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $xor.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$constmap:63821fe1682050c9271259d433a2dc1ea380438e$paramod$49d681ea06dc393300e89e053fdf6293d075bc05\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:b5d59b8994de2330dad281aa9498651e7a356696$paramod$8ef768ff46dceeb08a814a9eb5d794c1bd87354f\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Running "alumacc" on wrapper $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=25:Y_WIDTH=25:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=25:Y_WIDTH=25:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=25:Y_WIDTH=25:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=26:B_SIGNED=0:B_WIDTH=26:Y_WIDTH=26:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=26:B_SIGNED=0:B_WIDTH=26:Y_WIDTH=26:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=26:B_SIGNED=0:B_WIDTH=26:Y_WIDTH=26:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=28:Y_WIDTH=28:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=28:Y_WIDTH=28:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=28:Y_WIDTH=28:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=5:B_SIGNED=0:B_WIDTH=5:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$constmap:385d7f6387806d43d835e83bd5ede1f69672f116$paramod$590aed24860c170f91752de0a1d81ad5c26763bb\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Running "alumacc" on wrapper $extern:wrap:$gt:A_SIGNED=0:A_WIDTH=3:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$gt:A_SIGNED=0:A_WIDTH=3:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$gt:A_SIGNED=0:A_WIDTH=3:B_SIGNED=0:B_WIDTH=3:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=25:B_SIGNED=0:B_WIDTH=25:Y_WIDTH=25:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=25:B_SIGNED=0:B_WIDTH=25:Y_WIDTH=25:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=25:B_SIGNED=0:B_WIDTH=25:Y_WIDTH=25:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=6:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=6:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=6:B_SIGNED=0:B_WIDTH=6:Y_WIDTH=6:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$constmap:13bfeae1fdd8339488f5e9de822df1712d81ec51$paramod$f377f7dd4d619d5d6c5e02d26efbbd42bb842fca\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Running "alumacc" on wrapper $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=24:B_SIGNED=0:B_WIDTH=24:Y_WIDTH=48:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=24:B_SIGNED=0:B_WIDTH=24:Y_WIDTH=48:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=24:B_SIGNED=0:B_WIDTH=24:Y_WIDTH=48:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$d629d85c8826a74239b9178d1930215a43b0ceb0\_90_pmux for cells of type $pmux.
Using template $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$e82d3fc1811c5751348a3964470632b35a435fc7\_90_alu for cells of type $alu.
Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\_90_alu for cells of type $alu.
Using template $paramod$484d51534650924b7ed4c69e46eed3a56904771f\_90_alu for cells of type $alu.
Using template $paramod$3d4d857737ce5ee764ebe220e87ff73b66d6d0ad\_90_alu for cells of type $alu.
Using template $paramod$a7ecfa730f7b429cdd2d19291637694b0937162d\_90_alu for cells of type $alu.
Using template $paramod$f02bbbf710bba6238f4bdfa41b3051acfe2064a8\_90_alu for cells of type $alu.
Using template $paramod$d2fa05d38998afabc6d4f34471305d0af4b8b2df\_90_alu for cells of type $alu.
Using template $paramod$b7e1f79258b87e4a83a116a743fd12e845b7ee99\_90_alu for cells of type $alu.
Using template $paramod$7af98a8d3d01ff58dee4212ab52569c379e064a1\_90_alu for cells of type $alu.
Using template $paramod$b428551475981eb3841439c41ff02dfe9ed0c0f2\_90_alu for cells of type $alu.
Using template $paramod$b18e16801adf491a64caa0542270798e5d4ac6b6\_90_alu for cells of type $alu.
Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_90_alu for cells of type $alu.
Using template $paramod$4868d58a04723871777326409a611fa912defcd8\_90_alu for cells of type $alu.
Using template $paramod$00298f3f8094950cb9a5ff2fda48d0d8bde8806c\_90_alu for cells of type $alu.
Using extmapper maccmap for cells of type $macc.
add { 1'1 \result_fraction__3 } * { 1'1 \sub_32326 [17:0] \approx_fraction__4 [4:0] } (24x24 bits, unsigned)
add { 1'1 \result_fraction__5 } * { 1'1 \sub_32326 [17:0] \approx_fraction__4 [4:0] } (24x24 bits, unsigned)
add { 1'1 \sub_32326 [17:0] \approx_fraction__4 [4:0] } * { 1'1 \result_fraction__11 } (24x24 bits, unsigned)
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000011000 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001000 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001010 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001001 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000011011 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000011001 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000011010 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000011100 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000101 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000110 for cells of type $lcu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000110000 for cells of type $fa.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000101111 for cells of type $fa.
Using template $paramod$88aad6f8473fb7e4e5fbfb8335ddebad03429eaa\_90_alu for cells of type $alu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000110000 for cells of type $lcu.
No more expansions possible.
<suppressed ~7705 debug messages>

6. Executing ABC pass (technology mapping using ABC).

6.1. Extracting gate netlist of module `\__float32__fast_rsqrt' to `<abc-temp-dir>/input.blif'..
Extracted 28417 gates and 28452 wires to a netlist network with 32 inputs and 32 outputs.

6.1.1. Executing ABC.

stderr:

Attempted Command

docker run --name xlsynth-bvc-run-3ea7f9c3648fb1a2-2098204-81 --rm --pull never --network none -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/artifacts/ae/7f/ae7fe81cbe376de01d05941696c431dcd9a86fecad92efe9cf10e93e33a13dfc/payload/result.v:/inputs/input.v:ro -v /home/cdleary/proj/xlsynth-bvc/flows/yosys_to_aig.ys:/inputs/flow.ys:ro -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/.staging/3ea7f9c3648fb1a27a9b963a9af87416ce6e7bf0270e1f8231df8c83a4356281-2098204-1771562810868698671/payload:/outputs -e READ_VERILOG_FLAGS= -e VERILOG_TOP_MODULE_NAME=__float32__fast_rsqrt xlsynth-bvc-yosys-abc:ubuntu24.04 bash -lc

Action JSON

{
  "action": "combo_verilog_to_yosys_abc_aig",
  "verilog_action_id": "ae7fe81cbe376de01d05941696c431dcd9a86fecad92efe9cf10e93e33a13dfc",
  "verilog_top_module_name": "__float32__fast_rsqrt",
  "yosys_script_ref": {
    "path": "flows/yosys_to_aig.ys",
    "sha256": "b96ea6e2f96ce4442a7370366c13c8f8a38cfd4e0fcc12860d940d3f0a28b07a"
  },
  "runtime": {
    "docker_image": "xlsynth-bvc-yosys-abc:ubuntu24.04",
    "dockerfile": "docker/yosys-abc.Dockerfile"
  }
}

Action 3ea7f9c3648fb1a27a9b963a9af87416ce6e7bf0270e1f8231df8c83a4356281

Summary

Upstream Dependencies

Failure

Action JSON

Action `3ea7f9c3648fb1a27a9b963a9af87416ce6e7bf0270e1f8231df8c83a4356281`