module __float32__to_int32(
  input wire [31:0] x,
  output wire [31:0] out
);
  wire [7:0] x_bexp__2;
  wire [7:0] exp;
  wire [8:0] add_437;
  wire [22:0] x_fraction__2;
  wire [8:0] neg_442;
  wire [31:0] effective_exp;
  wire [23:0] fraction_shift_bits;
  wire eq_450;
  wire ne_451;
  wire [31:0] fraction;
  wire [31:0] sel_466;
  wire exp_oob;
  wire x_sign__1;
  wire [31:0] INT_MAX;
  wire [31:0] INT_MIN;
  wire [31:0] result;
  wire [31:0] result__2;
  assign x_bexp__2 = x[30:23];
  assign exp = x_bexp__2 + 8'h81;
  assign add_437 = {{1{exp[7]}}, exp} + 9'h1e9;
  assign x_fraction__2 = x[22:0];
  assign neg_442 = -add_437;
  assign effective_exp = {{23{add_437[8]}}, add_437};
  assign fraction_shift_bits = {1'h1, x_fraction__2};
  assign eq_450 = x_bexp__2 == 8'hff;
  assign ne_451 = x_fraction__2 != 23'h00_0000;
  assign fraction = {9'h001, x_fraction__2};
  assign sel_466 = effective_exp[31] ? {8'h00, {{23{neg_442[8]}}, neg_442} >= 32'h0000_0018 ? 24'h00_0000 : fraction_shift_bits >> {{23{neg_442[8]}}, neg_442}} : ((effective_exp & {32{$signed(add_437) > $signed(9'h000)}}) >= 32'h0000_0020 ? 32'h0000_0000 : fraction << (effective_exp & {32{$signed(add_437) > $signed(9'h000)}}));
  assign exp_oob = $signed(exp) >= $signed(8'h1f);
  assign x_sign__1 = x[31:31];
  assign INT_MAX = 32'h7fff_ffff;
  assign INT_MIN = 32'h8000_0000;
  assign result = exp_oob | ~(~eq_450 | ne_451) ? (x_sign__1 ? INT_MIN : INT_MAX) : (x_bexp__2 == 8'h7f ? 32'h0000_0001 : sel_466) & {32{~(eq_450 & ne_451 | exp[7])}};
  assign result__2 = x_sign__1 ? -result : result;
  assign out = result__2;
endmodule