module __hfloat16__ldexp(
  input wire [15:0] f,
  input wire [31:0] e,
  output wire [15:0] out
);
  wire [4:0] f_bexp__1;
  wire eq_454;
  wire [4:0] add_455;
  wire [9:0] tuple_index_459;
  wire [32:0] e__1;
  wire [9:0] f__1_fraction;
  wire [32:0] MAX_EXPONENT;
  wire [4:0] BIAS;
  wire [32:0] MIN_EXPONENT;
  wire sgt_471;
  wire [4:0] add_472;
  wire slt_476;
  wire [4:0] result__2_bexp__1;
  wire eq_482;
  wire eq_483;
  wire f_sign;
  wire nor_491;
  wire [9:0] and_494;
  wire [15:0] result__5;
  assign f_bexp__1 = f[14:10];
  assign eq_454 = f_bexp__1 == 5'h00;
  assign add_455 = f_bexp__1 + 5'h11;
  assign tuple_index_459 = f[9:0];
  assign e__1 = {{1{e[31]}}, e} + {{28{add_455[4]}}, add_455};
  assign f__1_fraction = tuple_index_459 & {10{~eq_454}};
  assign MAX_EXPONENT = 33'h0_0000_000f;
  assign BIAS = 5'h0f;
  assign MIN_EXPONENT = 33'h1_ffff_fff2;
  assign sgt_471 = $signed(e__1) > $signed(MAX_EXPONENT);
  assign add_472 = e__1[4:0] + BIAS;
  assign slt_476 = $signed(e__1) < $signed(MIN_EXPONENT);
  assign result__2_bexp__1 = slt_476 ? {4'h0, e__1 == 33'h1_ffff_fff1 & f__1_fraction == 10'h3ff} : (sgt_471 ? 5'h1f : add_472);
  assign eq_482 = f_bexp__1 == 5'h1f;
  assign eq_483 = f__1_fraction == 10'h000;
  assign f_sign = f[15:15];
  assign nor_491 = ~(~eq_482 | eq_483);
  assign and_494 = tuple_index_459 & {10{~(result__2_bexp__1 == 5'h00 | slt_476 | sgt_471 | eq_454)}};
  assign result__5 = {~(nor_491 | ~f_sign), nor_491 ? 5'h1f : (eq_454 | eq_482 & eq_483 ? f_bexp__1 : result__2_bexp__1), nor_491 ? 10'h200 : and_494};
  assign out = result__5;
endmodule