module __float64__lte_2(
  input wire [63:0] x,
  input wire [63:0] y,
  output wire out
);
  function automatic priority_sel_1b_3way (input reg [2:0] sel, input reg case0, input reg case1, input reg case2, input reg default_value);
    begin
      casez (sel)
        3'b??1: begin
          priority_sel_1b_3way = case0;
        end
        3'b?10: begin
          priority_sel_1b_3way = case1;
        end
        3'b100: begin
          priority_sel_1b_3way = case2;
        end
        3'b000: begin
          priority_sel_1b_3way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_1b_3way = 1'dx;
        end
      endcase
    end
  endfunction
  wire [10:0] x_bexp__1;
  wire [10:0] literal_587;
  wire [10:0] y_bexp__1;
  wire eq_589;
  wire eq_590;
  wire [51:0] x_fraction__1;
  wire [51:0] y_fraction__2;
  wire [10:0] literal_597;
  wire [51:0] literal_598;
  wire x_sign__1;
  wire y_sign__2;
  wire [51:0] x__1_fraction__1;
  wire [51:0] y__1_fraction__1;
  wire eq_607;
  wire eq_exp;
  wire gt_fraction;
  wire and_611;
  wire and_612;
  wire and_614;
  wire gt_exp;
  wire nor_617;
  wire abs_gt;
  wire and_633;
  wire result;
  wire and_640;
  assign x_bexp__1 = x[62:52];
  assign literal_587 = 11'h000;
  assign y_bexp__1 = y[62:52];
  assign eq_589 = x_bexp__1 == literal_587;
  assign eq_590 = y_bexp__1 == literal_587;
  assign x_fraction__1 = x[51:0];
  assign y_fraction__2 = y[51:0];
  assign literal_597 = 11'h7ff;
  assign literal_598 = 52'h0_0000_0000_0000;
  assign x_sign__1 = x[63:63];
  assign y_sign__2 = y[63:63];
  assign x__1_fraction__1 = x_fraction__1 & {52{~eq_589}};
  assign y__1_fraction__1 = y_fraction__2 & {52{~eq_590}};
  assign eq_607 = x_sign__1 == y_sign__2;
  assign eq_exp = x_bexp__1 == y_bexp__1;
  assign gt_fraction = x__1_fraction__1 > y__1_fraction__1;
  assign and_611 = x_bexp__1 == literal_597 & x_fraction__1 != literal_598;
  assign and_612 = y_bexp__1 == literal_597 & y_fraction__2 != literal_598;
  assign and_614 = eq_589 & eq_590;
  assign gt_exp = x_bexp__1 > y_bexp__1;
  assign nor_617 = ~(and_611 | and_612);
  assign abs_gt = gt_exp | eq_exp & gt_fraction;
  assign and_633 = ~abs_gt & ~(nor_617 & (eq_607 & eq_exp & x__1_fraction__1 == y__1_fraction__1 | and_614));
  assign result = priority_sel_1b_3way({~(~x_sign__1 | y_sign__2), ~(x_sign__1 | ~y_sign__2), ~(x_sign__1 | y_sign__2)}, abs_gt, 1'h1, 1'h0, and_633);
  assign and_640 = ~(nor_617 & (eq_607 & eq_exp & x_fraction__1 == y_fraction__2 | and_614)) & ~(and_611 | and_612 | ~result);
  assign out = ~(and_611 | and_612 | and_640);
endmodule