Action `132315e92b79043d4db0fea4ef7208aabecbf533577149e9d4d10d91eff751a4`

Summary

state: not queued

kind: combo_verilog_to_yosys_abc_aig

subject: verilog=98c6ab205d75 top=__float64__mul

crate:v0.6.0dso:-driver:-

Upstream Dependencies

Role	Action ID	State	Kind	Subject	Output
`verilog_action_id`	`98c6ab205d75bee178649c0856e72588c18559a9c985eed1f7552dd32a98e0bc`	done	`ir_fn_to_combinational_verilog`	ir=3dccc793ae7f top=__float64__mul system_verilog=false	`verilog_file payload/result.v`

Failure

timeout at 2026-02-20T04:46:44.926217180+00:00 by unknown-host:2098204:web-runner-1

summary: TIMEOUT(300) docker run exceeded 300 seconds (container=xlsynth-bvc-run-132315e92b79043d-2098204-13)

TIMEOUT(300) docker run exceeded 300 seconds (container=xlsynth-bvc-run-132315e92b79043d-2098204-13)
command:
docker run --name xlsynth-bvc-run-132315e92b79043d-2098204-13 --rm --pull never --network none -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/artifacts/98/c6/98c6ab205d75bee178649c0856e72588c18559a9c985eed1f7552dd32a98e0bc/payload/result.v:/inputs/input.v:ro -v /home/cdleary/proj/xlsynth-bvc/flows/yosys_to_aig.ys:/inputs/flow.ys:ro -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/.staging/132315e92b79043d4db0fea4ef7208aabecbf533577149e9d4d10d91eff751a4-2098204-1771562504236468541/payload:/outputs -e READ_VERILOG_FLAGS= -e VERILOG_TOP_MODULE_NAME=__float64__mul xlsynth-bvc-yosys-abc:ubuntu24.04 bash -lc 
set -euo pipefail
{
  echo "read_verilog ${READ_VERILOG_FLAGS} /inputs/input.v"
  if [ -n "${VERILOG_TOP_MODULE_NAME:-}" ]; then
    echo "hierarchy -check -top ${VERILOG_TOP_MODULE_NAME}"
  fi
  echo "script /inputs/flow.ys"
  echo "write_aiger /outputs/result.aig"
} > /tmp/run.ys
yosys -s /tmp/run.ys
test -s /outputs/result.aig

cleanup: removed timed-out container
stdout:

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.33 (git sha1 2584903a060)


-- Executing script file `/tmp/run.ys' --

1. Executing Verilog-2005 frontend: /inputs/input.v
Parsing Verilog input from `/inputs/input.v' to AST representation.
Generating RTLIL representation for module `\__float64__mul'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \__float64__mul

2.2. Analyzing design hierarchy..
Top module:  \__float64__mul
Removed 0 unused modules.

-- Executing script file `/inputs/flow.ys' --

3. Executing PROC pass (convert processes to netlists).

3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 4 assignments to connections.

3.4. Executing PROC_INIT pass (extract init attributes).

3.5. Executing PROC_ARST pass (detect async resets in processes).

3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\__float64__mul.$proc$/inputs/input.v:0$62'.

3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\__float64__mul.\umul106b_53b_x_53b$func$/inputs/input.v:81$1.$result' from process `\__float64__mul.$proc$/inputs/input.v:0$62'.
No latch inferred for signal `\__float64__mul.\umul106b_53b_x_53b$func$/inputs/input.v:81$2.$result' from process `\__float64__mul.$proc$/inputs/input.v:0$62'.
No latch inferred for signal `\__float64__mul.\umul106b_53b_x_53b$func$/inputs/input.v:81$2.lhs' from process `\__float64__mul.$proc$/inputs/input.v:0$62'.
No latch inferred for signal `\__float64__mul.\umul106b_53b_x_53b$func$/inputs/input.v:81$2.rhs' from process `\__float64__mul.$proc$/inputs/input.v:0$62'.

3.9. Executing PROC_DFF pass (convert process syncs to FFs).

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `__float64__mul.$proc$/inputs/input.v:0$62'.
Cleaned up 0 empty switches.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float64__mul.
<suppressed ~5 debug messages>

4. Executing OPT pass (performing simple optimizations).

4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float64__mul.

4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__float64__mul'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \__float64__mul..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>

4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \__float64__mul.
Performed a total of 0 changes.

4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__float64__mul'.
Removed a total of 0 cells.

4.6. Executing OPT_DFF pass (perform DFF optimizations).

4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \__float64__mul..
Removed 0 unused cells and 41 unused wires.
<suppressed ~1 debug messages>

4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float64__mul.

4.9. Rerunning OPT passes. (Maybe there is more to do..)

4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \__float64__mul..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>

4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \__float64__mul.
Performed a total of 0 changes.

4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__float64__mul'.
Removed a total of 0 cells.

4.13. Executing OPT_DFF pass (perform DFF optimizations).

4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \__float64__mul..

4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float64__mul.

4.16. Finished OPT passes. (There is nothing left to do.)

5. Executing TECHMAP pass (map to technology primitives).

5.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

5.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $not.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=12:B_SIGNED=0:B_WIDTH=12:Y_WIDTH=12:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=12:B_SIGNED=0:B_WIDTH=12:Y_WIDTH=12:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=12:B_SIGNED=0:B_WIDTH=12:Y_WIDTH=12:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $and.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=13:B_SIGNED=0:B_WIDTH=13:Y_WIDTH=13:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=13:B_SIGNED=0:B_WIDTH=13:Y_WIDTH=13:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=13:B_SIGNED=0:B_WIDTH=13:Y_WIDTH=13:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$constmap:e0e01f7ddcba9d19aded95e7f57bfe7645705a05$paramod$f1a9710c138164a05ad8af9260868567b957cf5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using extmapper simplemap for cells of type $or.
Running "alumacc" on wrapper $extern:wrap:$le:A_SIGNED=1:A_WIDTH=13:B_SIGNED=1:B_WIDTH=13:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$le:A_SIGNED=1:A_WIDTH=13:B_SIGNED=1:B_WIDTH=13:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$le:A_SIGNED=1:A_WIDTH=13:B_SIGNED=1:B_WIDTH=13:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $reduce_bool.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=53:B_SIGNED=0:B_WIDTH=53:Y_WIDTH=53:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=53:B_SIGNED=0:B_WIDTH=53:Y_WIDTH=53:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=53:B_SIGNED=0:B_WIDTH=53:Y_WIDTH=53:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $xor.
Running "alumacc" on wrapper $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=53:B_SIGNED=0:B_WIDTH=53:Y_WIDTH=106:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=53:B_SIGNED=0:B_WIDTH=53:Y_WIDTH=106:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=53:B_SIGNED=0:B_WIDTH=53:Y_WIDTH=106:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$ee3d784672cdb1cb32d9a801a3af776716f16b74\_90_alu for cells of type $alu.
Using template $paramod$2780480d52179e2db572a6e5133edf36e733d32e\_90_alu for cells of type $alu.
Using template $paramod$381bfac1a8d048c2a82a5e9a8ba59722228aaa1f\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_or.
Using template $paramod$9a81d61ff9404693dfc8fc05c99b49687937fb66\_90_alu for cells of type $alu.
Using extmapper maccmap for cells of type $macc.
  add { 1'1 \x [51:0] } * { 1'1 \y [51:0] } (53x53 bits, unsigned)
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001100 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001101 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000110101 for cells of type $lcu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000001101010 for cells of type $fa.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000001101001 for cells of type $fa.
Using template $paramod$62e74e5d77aab722a53c83171bc352e6dd9d1500\_90_alu for cells of type $alu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000001101010 for cells of type $lcu.
No more expansions possible.
<suppressed ~2713 debug messages>

6. Executing ABC pass (technology mapping using ABC).

6.1. Extracting gate netlist of module `\__float64__mul' to `<abc-temp-dir>/input.blif'..
Extracted 35828 gates and 35958 wires to a netlist network with 128 inputs and 64 outputs.

6.1.1. Executing ABC.

stderr:

Attempted Command

docker run --name xlsynth-bvc-run-132315e92b79043d-2098204-13 --rm --pull never --network none -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/artifacts/98/c6/98c6ab205d75bee178649c0856e72588c18559a9c985eed1f7552dd32a98e0bc/payload/result.v:/inputs/input.v:ro -v /home/cdleary/proj/xlsynth-bvc/flows/yosys_to_aig.ys:/inputs/flow.ys:ro -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/.staging/132315e92b79043d4db0fea4ef7208aabecbf533577149e9d4d10d91eff751a4-2098204-1771562504236468541/payload:/outputs -e READ_VERILOG_FLAGS= -e VERILOG_TOP_MODULE_NAME=__float64__mul xlsynth-bvc-yosys-abc:ubuntu24.04 bash -lc

Action JSON

{
  "action": "combo_verilog_to_yosys_abc_aig",
  "verilog_action_id": "98c6ab205d75bee178649c0856e72588c18559a9c985eed1f7552dd32a98e0bc",
  "verilog_top_module_name": "__float64__mul",
  "yosys_script_ref": {
    "path": "flows/yosys_to_aig.ys",
    "sha256": "b96ea6e2f96ce4442a7370366c13c8f8a38cfd4e0fcc12860d940d3f0a28b07a"
  },
  "runtime": {
    "docker_image": "xlsynth-bvc-yosys-abc:ubuntu24.04",
    "dockerfile": "docker/yosys-abc.Dockerfile"
  }
}

Action 132315e92b79043d4db0fea4ef7208aabecbf533577149e9d4d10d91eff751a4

Summary

Upstream Dependencies

Failure

Action JSON

Action `132315e92b79043d4db0fea4ef7208aabecbf533577149e9d4d10d91eff751a4`