Action `10c20df1ce19768f8a2a806219dbe9e5597267f7c92b141f7d4c267f5317c1ea`

Summary

state: not queued

kind: combo_verilog_to_yosys_abc_aig

subject: verilog=7c8c488dd7b7 top=__float64__fma

crate:v0.13.0dso:-driver:-

Upstream Dependencies

Role	Action ID	State	Kind	Subject	Output
`verilog_action_id`	`7c8c488dd7b7ea76598fa568334ef17fff98d79fd930d0a01f3b817ca9e5b5d6`	done	`ir_fn_to_combinational_verilog`	ir=cd1675f7d568 top=__float64__fma system_verilog=false	`verilog_file payload/result.v`

Failure

timeout at 2026-02-20T04:46:52.340998141+00:00 by unknown-host:2098204:web-runner-8

summary: TIMEOUT(300) docker run exceeded 300 seconds (container=xlsynth-bvc-run-10c20df1ce19768f-2098204-45)

TIMEOUT(300) docker run exceeded 300 seconds (container=xlsynth-bvc-run-10c20df1ce19768f-2098204-45)
command:
docker run --name xlsynth-bvc-run-10c20df1ce19768f-2098204-45 --rm --pull never --network none -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/artifacts/7c/8c/7c8c488dd7b7ea76598fa568334ef17fff98d79fd930d0a01f3b817ca9e5b5d6/payload/result.v:/inputs/input.v:ro -v /home/cdleary/proj/xlsynth-bvc/flows/yosys_to_aig.ys:/inputs/flow.ys:ro -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/.staging/10c20df1ce19768f8a2a806219dbe9e5597267f7c92b141f7d4c267f5317c1ea-2098204-1771562511883599048/payload:/outputs -e READ_VERILOG_FLAGS= -e VERILOG_TOP_MODULE_NAME=__float64__fma xlsynth-bvc-yosys-abc:ubuntu24.04 bash -lc
set -euo pipefail
{
echo "read_verilog ${READ_VERILOG_FLAGS} /inputs/input.v"
if [ -n "${VERILOG_TOP_MODULE_NAME:-}" ]; then
echo "hierarchy -check -top ${VERILOG_TOP_MODULE_NAME}"
fi
echo "script /inputs/flow.ys"
echo "write_aiger /outputs/result.aig"
} > /tmp/run.ys
yosys -s /tmp/run.ys
test -s /outputs/result.aig

cleanup: removed timed-out container
stdout:

/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/

Yosys 0.33 (git sha1 2584903a060)

-- Executing script file `/tmp/run.ys' --

1. Executing Verilog-2005 frontend: /inputs/input.v
Parsing Verilog input from `/inputs/input.v' to AST representation.
Generating RTLIL representation for module `\__float64__fma'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module: \__float64__fma

2.2. Analyzing design hierarchy..
Top module: \__float64__fma
Removed 0 unused modules.

-- Executing script file `/inputs/flow.ys' --

3. Executing PROC pass (convert processes to netlists).

3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed 1 dead cases from process $proc$/inputs/input.v:0$1063 in module __float64__fma.
Marked 1 switch rules as full_case in process $proc$/inputs/input.v:0$1063 in module __float64__fma.
Removed a total of 1 dead cases.

3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 10 assignments to connections.

3.4. Executing PROC_INIT pass (extract init attributes).

3.5. Executing PROC_ARST pass (detect async resets in processes).

3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\__float64__fma.$proc$/inputs/input.v:0$1063'.
1/1: $1\priority_sel_1b_2way$func$/inputs/input.v:273$4.$result[0:0]$1071
Creating decoders for process `\__float64__fma.$proc$/inputs/input.v:0$1057'.

3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\__float64__fma.\priority_sel_1b_2way$func$/inputs/input.v:273$2.$result' from process `\__float64__fma.$proc$/inputs/input.v:0$1063'.
No latch inferred for signal `\__float64__fma.\priority_sel_1b_2way$func$/inputs/input.v:273$4.$result' from process `\__float64__fma.$proc$/inputs/input.v:0$1063'.
No latch inferred for signal `\__float64__fma.\priority_sel_1b_2way$func$/inputs/input.v:273$4.sel' from process `\__float64__fma.$proc$/inputs/input.v:0$1063'.
No latch inferred for signal `\__float64__fma.\priority_sel_1b_2way$func$/inputs/input.v:273$4.case0' from process `\__float64__fma.$proc$/inputs/input.v:0$1063'.
No latch inferred for signal `\__float64__fma.\priority_sel_1b_2way$func$/inputs/input.v:273$4.case1' from process `\__float64__fma.$proc$/inputs/input.v:0$1063'.
No latch inferred for signal `\__float64__fma.\priority_sel_1b_2way$func$/inputs/input.v:273$4.default_value' from process `\__float64__fma.$proc$/inputs/input.v:0$1063'.
No latch inferred for signal `\__float64__fma.\umul106b_53b_x_53b$func$/inputs/input.v:170$1.$result' from process `\__float64__fma.$proc$/inputs/input.v:0$1057'.
No latch inferred for signal `\__float64__fma.\umul106b_53b_x_53b$func$/inputs/input.v:170$3.$result' from process `\__float64__fma.$proc$/inputs/input.v:0$1057'.
No latch inferred for signal `\__float64__fma.\umul106b_53b_x_53b$func$/inputs/input.v:170$3.lhs' from process `\__float64__fma.$proc$/inputs/input.v:0$1057'.
No latch inferred for signal `\__float64__fma.\umul106b_53b_x_53b$func$/inputs/input.v:170$3.rhs' from process `\__float64__fma.$proc$/inputs/input.v:0$1057'.

3.9. Executing PROC_DFF pass (convert process syncs to FFs).

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\__float64__fma.$proc$/inputs/input.v:0$1063'.
Removing empty process `__float64__fma.$proc$/inputs/input.v:0$1063'.
Removing empty process `__float64__fma.$proc$/inputs/input.v:0$1057'.
Cleaned up 1 empty switch.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float64__fma.
<suppressed ~175 debug messages>

4. Executing OPT pass (performing simple optimizations).

4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float64__fma.

4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__float64__fma'.
<suppressed ~24 debug messages>
Removed a total of 8 cells.

4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \__float64__fma..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Replacing known input bits on port B of cell $ternary$/inputs/input.v:200$39: \full_product -> { 1'1 \full_product [104:0] }
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~18 debug messages>

4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \__float64__fma.
Performed a total of 0 changes.

4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__float64__fma'.
Removed a total of 0 cells.

4.6. Executing OPT_DFF pass (perform DFF optimizations).

4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \__float64__fma..
Removed 4 unused cells and 280 unused wires.
<suppressed ~5 debug messages>

4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float64__fma.

4.9. Rerunning OPT passes. (Maybe there is more to do..)

4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \__float64__fma..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~18 debug messages>

4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \__float64__fma.
Performed a total of 0 changes.

4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\__float64__fma'.
Removed a total of 0 cells.

4.13. Executing OPT_DFF pass (perform DFF optimizations).

4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \__float64__fma..

4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module __float64__fma.

4.16. Finished OPT passes. (There is nothing left to do.)

5. Executing TECHMAP pass (map to technology primitives).

5.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

5.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $not.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=12:B_SIGNED=0:B_WIDTH=12:Y_WIDTH=12:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=12:B_SIGNED=0:B_WIDTH=12:Y_WIDTH=12:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=12:B_SIGNED=0:B_WIDTH=12:Y_WIDTH=12:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $eq.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=13:B_SIGNED=0:B_WIDTH=13:Y_WIDTH=13:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=13:B_SIGNED=0:B_WIDTH=13:Y_WIDTH=13:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=13:B_SIGNED=0:B_WIDTH=13:Y_WIDTH=13:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
Running "alumacc" on wrapper $extern:wrap:$le:A_SIGNED=1:A_WIDTH=13:B_SIGNED=1:B_WIDTH=13:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$le:A_SIGNED=1:A_WIDTH=13:B_SIGNED=1:B_WIDTH=13:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$le:A_SIGNED=1:A_WIDTH=13:B_SIGNED=1:B_WIDTH=13:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $xor.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=12:B_SIGNED=0:B_WIDTH=12:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=12:B_SIGNED=0:B_WIDTH=12:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=12:B_SIGNED=0:B_WIDTH=12:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=12:Y_WIDTH=12:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=12:Y_WIDTH=12:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=12:Y_WIDTH=12:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$constmap:44f3e0ee27f0afa6d17ca6da2225b36f2da678b1$paramod$1caceb394f2cab44a3648a99c02e6fa80797d28c\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:c48fc8c3c3bc2086a7e9e282f1c718b25cf73026$paramod$4ed153717dc08d039339935c5ea2077523cdff15\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using extmapper simplemap for cells of type $reduce_bool.
Using template $paramod$constmap:d71b78b783fa1ccc0f5e609b7cba5467725e67c9$paramod$2bc550224115f4d935e0054e5d0cc19811cb5dbe\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Analyzing pattern of constant bits for this cell:
Constant input on bit 0 of port A: 1'0
Constant input on bit 1 of port A: 1'0
Constant input on bit 2 of port A: 1'0
Constant input on bit 3 of port A: 1'0
Constant input on bit 4 of port A: 1'0
Constant input on bit 5 of port A: 1'0
Constant input on bit 6 of port A: 1'0
Constant input on bit 7 of port A: 1'0
Constant input on bit 8 of port A: 1'0
Constant input on bit 9 of port A: 1'0
Constant input on bit 10 of port A: 1'0
Constant input on bit 11 of port A: 1'0
Constant input on bit 12 of port A: 1'0
Constant input on bit 13 of port A: 1'0
Constant input on bit 14 of port A: 1'0
Constant input on bit 15 of port A: 1'0
Constant input on bit 16 of port A: 1'0
Constant input on bit 17 of port A: 1'0
Constant input on bit 18 of port A: 1'0
Constant input on bit 19 of port A: 1'0
Constant input on bit 20 of port A: 1'0
Constant input on bit 21 of port A: 1'0
Constant input on bit 22 of port A: 1'0
Constant input on bit 23 of port A: 1'0
Constant input on bit 24 of port A: 1'0
Constant input on bit 25 of port A: 1'0
Constant input on bit 26 of port A: 1'0
Constant input on bit 27 of port A: 1'0
Constant input on bit 28 of port A: 1'0
Constant input on bit 29 of port A: 1'0
Constant input on bit 30 of port A: 1'0
Constant input on bit 31 of port A: 1'0
Constant input on bit 32 of port A: 1'0
Constant input on bit 33 of port A: 1'0
Constant input on bit 34 of port A: 1'0
Constant input on bit 35 of port A: 1'0
Constant input on bit 36 of port A: 1'0
Constant input on bit 37 of port A: 1'0
Constant input on bit 38 of port A: 1'0
Constant input on bit 39 of port A: 1'0
Constant input on bit 40 of port A: 1'0
Constant input on bit 41 of port A: 1'0
Constant input on bit 42 of port A: 1'0
Constant input on bit 43 of port A: 1'0
Constant input on bit 44 of port A: 1'0
Constant input on bit 45 of port A: 1'0
Constant input on bit 46 of port A: 1'0
Constant input on bit 47 of port A: 1'0
Constant input on bit 48 of port A: 1'0
Constant input on bit 49 of port A: 1'0
Constant input on bit 50 of port A: 1'0
Constant input on bit 51 of port A: 1'0
Constant input on bit 52 of port A: 1'0
Constant input on bit 53 of port A: 1'0
Constant input on bit 54 of port A: 1'0
Constant input on bit 55 of port A: 1'0
Constant input on bit 56 of port A: 1'0
Constant input on bit 57 of port A: 1'0
Constant input on bit 58 of port A: 1'0
Constant input on bit 59 of port A: 1'0
Constant input on bit 60 of port A: 1'0
Constant input on bit 61 of port A: 1'0
Constant input on bit 62 of port A: 1'0
Constant input on bit 63 of port A: 1'0
Constant input on bit 64 of port A: 1'0
Constant input on bit 65 of port A: 1'0
Constant input on bit 66 of port A: 1'0
Constant input on bit 67 of port A: 1'0
Constant input on bit 68 of port A: 1'0
Constant input on bit 69 of port A: 1'0
Constant input on bit 70 of port A: 1'0
Constant input on bit 71 of port A: 1'0
Constant input on bit 72 of port A: 1'0
Constant input on bit 73 of port A: 1'0
Constant input on bit 74 of port A: 1'0
Constant input on bit 75 of port A: 1'0
Constant input on bit 76 of port A: 1'0
Constant input on bit 77 of port A: 1'0
Constant input on bit 78 of port A: 1'0
Constant input on bit 79 of port A: 1'0
Constant input on bit 80 of port A: 1'0
Constant input on bit 81 of port A: 1'0
Constant input on bit 82 of port A: 1'0
Constant input on bit 83 of port A: 1'0
Constant input on bit 84 of port A: 1'0
Constant input on bit 85 of port A: 1'0
Constant input on bit 86 of port A: 1'0
Constant input on bit 87 of port A: 1'0
Constant input on bit 88 of port A: 1'0
Constant input on bit 89 of port A: 1'0
Constant input on bit 90 of port A: 1'0
Constant input on bit 91 of port A: 1'0
Constant input on bit 92 of port A: 1'0
Constant input on bit 93 of port A: 1'0
Constant input on bit 94 of port A: 1'0
Constant input on bit 95 of port A: 1'0
Constant input on bit 96 of port A: 1'0
Constant input on bit 97 of port A: 1'0
Constant input on bit 98 of port A: 1'0
Constant input on bit 99 of port A: 1'0
Constant input on bit 100 of port A: 1'0
Constant input on bit 101 of port A: 1'0
Constant input on bit 102 of port A: 1'0
Constant input on bit 103 of port A: 1'0
Constant input on bit 104 of port A: 1'0
Constant input on bit 105 of port A: 1'0
Constant input on bit 106 of port A: 1'0
Creating constmapped module `$paramod$constmap:6af0fffdc33e552d4e20719a550f665202f8d602$paramod$2bc550224115f4d935e0054e5d0cc19811cb5dbe\_90_shift_ops_shr_shl_sshl_sshr'.

5.28. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$constmap:6af0fffdc33e552d4e20719a550f665202f8d602$paramod$2bc550224115f4d935e0054e5d0cc19811cb5dbe\_90_shift_ops_shr_shl_sshl_sshr..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
<suppressed ~7192 debug messages>

5.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$constmap:6af0fffdc33e552d4e20719a550f665202f8d602$paramod$2bc550224115f4d935e0054e5d0cc19811cb5dbe\_90_shift_ops_shr_shl_sshl_sshr.
<suppressed ~3509 debug messages>
Removed 0 unused cells and 23 unused wires.
Using template $paramod$constmap:6af0fffdc33e552d4e20719a550f665202f8d602$paramod$2bc550224115f4d935e0054e5d0cc19811cb5dbe\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Running "alumacc" on wrapper $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=161:Y_WIDTH=161:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=161:Y_WIDTH=161:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=161:Y_WIDTH=161:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=162:B_SIGNED=0:B_WIDTH=162:Y_WIDTH=162:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=162:B_SIGNED=0:B_WIDTH=162:Y_WIDTH=162:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=162:B_SIGNED=0:B_WIDTH=162:Y_WIDTH=162:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $logic_and.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=9:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=9:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=9:B_SIGNED=0:B_WIDTH=9:Y_WIDTH=9:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=161:B_SIGNED=0:B_WIDTH=161:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=161:B_SIGNED=0:B_WIDTH=161:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:A_SIGNED=0:A_WIDTH=161:B_SIGNED=0:B_WIDTH=161:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$constmap:029a132419848f9eb2017b907ddb0dd342b08ab3$paramod$8855bab3b4a9c7c757604eb1adc0ba6a98c92d3b\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=54:B_SIGNED=0:B_WIDTH=54:Y_WIDTH=54:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=54:B_SIGNED=0:B_WIDTH=54:Y_WIDTH=54:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=54:B_SIGNED=0:B_WIDTH=54:Y_WIDTH=54:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$gt:A_SIGNED=0:A_WIDTH=107:B_SIGNED=0:B_WIDTH=107:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$gt:A_SIGNED=0:A_WIDTH=107:B_SIGNED=0:B_WIDTH=107:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$gt:A_SIGNED=0:A_WIDTH=107:B_SIGNED=0:B_WIDTH=107:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=8:B_SIGNED=0:B_WIDTH=8:Y_WIDTH=8:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $reduce_and.
Running "alumacc" on wrapper $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=53:B_SIGNED=0:B_WIDTH=53:Y_WIDTH=106:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=53:B_SIGNED=0:B_WIDTH=53:Y_WIDTH=106:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=53:B_SIGNED=0:B_WIDTH=53:Y_WIDTH=106:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$d629d85c8826a74239b9178d1930215a43b0ceb0\_90_pmux for cells of type $pmux.
Using template $paramod$ee3d784672cdb1cb32d9a801a3af776716f16b74\_90_alu for cells of type $alu.
Using template $paramod$2780480d52179e2db572a6e5133edf36e733d32e\_90_alu for cells of type $alu.
Using template $paramod$381bfac1a8d048c2a82a5e9a8ba59722228aaa1f\_90_alu for cells of type $alu.
Using template $paramod$ce6e0bffdb8605e70c2145339a50927e2d751e17\_90_alu for cells of type $alu.
Using template $paramod$4b47833e715a6ffa76f34de785c674179bd00a99\_90_alu for cells of type $alu.
Using template $paramod$92652ebc61563a3135d6250f55e0825ca3eec5cb\_90_alu for cells of type $alu.
Using template $paramod$d2fa05d38998afabc6d4f34471305d0af4b8b2df\_90_alu for cells of type $alu.
Using template $paramod$118ddd0be44aa4734c568625db6d503b7fe8ed6c\_90_alu for cells of type $alu.
Using template $paramod$95803b2f2a0a67ebc594f50cf9cd7d672cce8582\_90_alu for cells of type $alu.
Using template $paramod$09f403cfbd36b9676b6f721e3b02a2f02d681c29\_90_alu for cells of type $alu.
Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\_90_alu for cells of type $alu.
Using extmapper maccmap for cells of type $macc.
add { 1'1 \a [51:0] } * { 1'1 \b [51:0] } (53x53 bits, unsigned)
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001100 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001101 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000010100001 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000010100010 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001001 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000110110 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000001101011 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001000 for cells of type $lcu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000001101010 for cells of type $fa.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000001101001 for cells of type $fa.
Using template $paramod$62e74e5d77aab722a53c83171bc352e6dd9d1500\_90_alu for cells of type $alu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000001101010 for cells of type $lcu.
No more expansions possible.
<suppressed ~11153 debug messages>

6. Executing ABC pass (technology mapping using ABC).

6.1. Extracting gate netlist of module `\__float64__fma' to `<abc-temp-dir>/input.blif'..
Extracted 71509 gates and 71704 wires to a netlist network with 192 inputs and 64 outputs.

6.1.1. Executing ABC.

stderr:

Attempted Command

docker run --name xlsynth-bvc-run-10c20df1ce19768f-2098204-45 --rm --pull never --network none -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/artifacts/7c/8c/7c8c488dd7b7ea76598fa568334ef17fff98d79fd930d0a01f3b817ca9e5b5d6/payload/result.v:/inputs/input.v:ro -v /home/cdleary/proj/xlsynth-bvc/flows/yosys_to_aig.ys:/inputs/flow.ys:ro -v /home/cdleary/proj/xlsynth-bvc/bvc-artifacts/.staging/10c20df1ce19768f8a2a806219dbe9e5597267f7c92b141f7d4c267f5317c1ea-2098204-1771562511883599048/payload:/outputs -e READ_VERILOG_FLAGS= -e VERILOG_TOP_MODULE_NAME=__float64__fma xlsynth-bvc-yosys-abc:ubuntu24.04 bash -lc

Action JSON

{
  "action": "combo_verilog_to_yosys_abc_aig",
  "verilog_action_id": "7c8c488dd7b7ea76598fa568334ef17fff98d79fd930d0a01f3b817ca9e5b5d6",
  "verilog_top_module_name": "__float64__fma",
  "yosys_script_ref": {
    "path": "flows/yosys_to_aig.ys",
    "sha256": "b96ea6e2f96ce4442a7370366c13c8f8a38cfd4e0fcc12860d940d3f0a28b07a"
  },
  "runtime": {
    "docker_image": "xlsynth-bvc-yosys-abc:ubuntu24.04",
    "dockerfile": "docker/yosys-abc.Dockerfile"
  }
}

Action 10c20df1ce19768f8a2a806219dbe9e5597267f7c92b141f7d4c267f5317c1ea

Summary

Upstream Dependencies

Failure

Action JSON

Action `10c20df1ce19768f8a2a806219dbe9e5597267f7c92b141f7d4c267f5317c1ea`