module __bfloat16__add(
  input wire [15:0] x,
  input wire [15:0] y,
  output wire [15:0] out
);
  function automatic [1:0] priority_sel_2b_2way (input reg [1:0] sel, input reg [1:0] case0, input reg [1:0] case1, input reg [1:0] default_value);
    begin
      casez (sel)
        2'b?1: begin
          priority_sel_2b_2way = case0;
        end
        2'b10: begin
          priority_sel_2b_2way = case1;
        end
        2'b00: begin
          priority_sel_2b_2way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_2b_2way = 2'dx;
        end
      endcase
    end
  endfunction
  function automatic priority_sel_1b_2way (input reg [1:0] sel, input reg case0, input reg case1, input reg default_value);
    begin
      casez (sel)
        2'b?1: begin
          priority_sel_1b_2way = case0;
        end
        2'b10: begin
          priority_sel_1b_2way = case1;
        end
        2'b00: begin
          priority_sel_1b_2way = default_value;
        end
        default: begin
          // Propagate X
          priority_sel_1b_2way = 1'dx;
        end
      endcase
    end
  endfunction
  wire [7:0] y_bexp__1;
  wire literal_27750;
  wire [7:0] x_bexp__1;
  wire [7:0] y_bexpnot;
  wire [8:0] x_bexp_extended__1;
  wire [8:0] y_bexpnot_extended;
  wire [8:0] full_result;
  wire overflow_detected;
  wire [6:0] tuple_index_27757;
  wire [6:0] tuple_index_27758;
  wire [7:0] x_bexp;
  wire [7:0] literal_27760;
  wire [7:0] y_bexp;
  wire literal_27762;
  wire [6:0] x_fraction;
  wire [6:0] y_fraction;
  wire nc;
  wire [7:0] fraction_x;
  wire [7:0] fraction_y;
  wire [7:0] sign_ext_27771;
  wire [7:0] narrowed_result;
  wire [7:0] x_bexpor_mask;
  wire [6:0] literal_27774;
  wire tuple_index_27775;
  wire tuple_index_27776;
  wire [7:0] fraction_x__1;
  wire [7:0] fraction_y__1;
  wire [2:0] xddend_x__1_squeezed_const_lsb_bits;
  wire [7:0] result;
  wire x_sign;
  wire y_sign;
  wire [8:0] wide_x_squeezed;
  wire [10:0] wide_y_shift_bits;
  wire [7:0] shift;
  wire [10:0] shrl_27790;
  wire [11:0] shll_27792;
  wire [8:0] xddend_x__1_squeezed;
  wire [1:0] literal_27794;
  wire [9:0] add_27802;
  wire sticky;
  wire [11:0] concat_27808;
  wire [11:0] xbs_fraction;
  wire carry_bit;
  wire nor_27829;
  wire nor_27831;
  wire and_27842;
  wire nor_27838;
  wire nor_27839;
  wire and_27855;
  wire and_27851;
  wire [2:0] concat_27863;
  wire [2:0] concat_27862;
  wire [3:0] concat_27867;
  wire [3:0] leading_zeroes;
  wire [12:0] cancel_fraction;
  wire [10:0] cancel_fraction__1;
  wire [10:0] carry_fraction__1;
  wire [10:0] shifted_fraction;
  wire [2:0] normal_chunk;
  wire [2:0] fraction_shift__3;
  wire [1:0] half_way_chunk;
  wire do_round_up;
  wire [8:0] add_27887;
  wire rounding_carry;
  wire [8:0] add_27900;
  wire [4:0] sub_27901;
  wire fraction_is_zero;
  wire [9:0] wide_exponent_associative_element;
  wire [9:0] wide_exponent_associative_element__1;
  wire [9:0] wide_exponent;
  wire [9:0] wide_exponent__1;
  wire [7:0] MAX_EXPONENT;
  wire [8:0] wide_exponent__2;
  wire eq_27915;
  wire eq_27916;
  wire eq_27917;
  wire eq_27918;
  wire [2:0] fraction_shift__2;
  wire is_operand_inf;
  wire and_reduce_27936;
  wire has_pos_inf;
  wire has_neg_inf;
  wire [11:0] rounded_fraction;
  wire [2:0] fraction_shift__1;
  wire [11:0] shrl_27949;
  wire is_result_nan;
  wire result_sign;
  wire [6:0] result_fraction;
  wire [6:0] sign_ext_27955;
  wire result_sign__1;
  wire [6:0] result_fraction__3;
  wire [6:0] FRACTION_HIGH_BIT;
  wire result_sign__2;
  wire [7:0] result_exponent__2;
  wire [6:0] result_fraction__4;
  assign y_bexp__1 = y[14:7];
  assign literal_27750 = 1'h0;
  assign x_bexp__1 = x[14:7];
  assign y_bexpnot = ~y_bexp__1;
  assign x_bexp_extended__1 = {literal_27750, x_bexp__1};
  assign y_bexpnot_extended = {literal_27750, y_bexpnot};
  assign full_result = x_bexp_extended__1 + y_bexpnot_extended;
  assign overflow_detected = full_result[8];
  assign tuple_index_27757 = y[6:0];
  assign tuple_index_27758 = x[6:0];
  assign x_bexp = overflow_detected ? x_bexp__1 : y_bexp__1;
  assign literal_27760 = 8'h00;
  assign y_bexp = overflow_detected ? y_bexp__1 : x_bexp__1;
  assign literal_27762 = 1'h1;
  assign x_fraction = overflow_detected ? tuple_index_27758 : tuple_index_27757;
  assign y_fraction = overflow_detected ? tuple_index_27757 : tuple_index_27758;
  assign nc = ~overflow_detected;
  assign fraction_x = {literal_27762, x_fraction};
  assign fraction_y = {literal_27762, y_fraction};
  assign sign_ext_27771 = {8{y_bexp != literal_27760}};
  assign narrowed_result = full_result[7:0];
  assign x_bexpor_mask = {8{nc}};
  assign literal_27774 = 7'h00;
  assign tuple_index_27775 = y[15:15];
  assign tuple_index_27776 = x[15:15];
  assign fraction_x__1 = fraction_x & {8{x_bexp != literal_27760}};
  assign fraction_y__1 = fraction_y & sign_ext_27771;
  assign xddend_x__1_squeezed_const_lsb_bits = 3'h0;
  assign result = narrowed_result ^ x_bexpor_mask;
  assign x_sign = overflow_detected ? tuple_index_27776 : tuple_index_27775;
  assign y_sign = overflow_detected ? tuple_index_27775 : tuple_index_27776;
  assign wide_x_squeezed = {literal_27750, fraction_x__1};
  assign wide_y_shift_bits = {fraction_y__1, xddend_x__1_squeezed_const_lsb_bits};
  assign shift = result + {literal_27774, overflow_detected};
  assign shrl_27790 = shift >= 8'h0b ? 11'h000 : wide_y_shift_bits >> shift;
  assign shll_27792 = shift >= 8'h0c ? 12'h000 : 12'hfff << shift;
  assign xddend_x__1_squeezed = x_sign ^ y_sign ? -wide_x_squeezed : wide_x_squeezed;
  assign literal_27794 = 2'h0;
  assign add_27802 = {{1{xddend_x__1_squeezed[8]}}, xddend_x__1_squeezed} + {literal_27794, shrl_27790[10:3]};
  assign sticky = ~({literal_27750, ~y_fraction} | ~sign_ext_27771 | shll_27792[10:3]) != literal_27760;
  assign concat_27808 = {add_27802[8:0], shrl_27790[2:1], shrl_27790[0] | sticky};
  assign xbs_fraction = add_27802[9] ? -concat_27808 : concat_27808;
  assign carry_bit = xbs_fraction[11];
  assign nor_27829 = ~(xbs_fraction[9] | xbs_fraction[8]);
  assign nor_27831 = ~(xbs_fraction[5] | xbs_fraction[4]);
  assign and_27842 = ~(carry_bit | xbs_fraction[10]) & nor_27829;
  assign nor_27838 = ~(xbs_fraction[1] | xbs_fraction[0]);
  assign nor_27839 = ~(xbs_fraction[3] | xbs_fraction[2]);
  assign and_27855 = ~(xbs_fraction[7] | xbs_fraction[6]) & nor_27831;
  assign and_27851 = nor_27839 & nor_27838;
  assign concat_27863 = {literal_27750, ~(carry_bit | xbs_fraction[10] | nor_27829) ? {literal_27762, ~(xbs_fraction[9] | ~xbs_fraction[8])} : {literal_27750, ~(carry_bit | ~xbs_fraction[10])}};
  assign concat_27862 = {literal_27762, ~(xbs_fraction[7] | xbs_fraction[6] | nor_27831) ? {literal_27762, ~(xbs_fraction[5] | ~xbs_fraction[4])} : {literal_27750, ~(xbs_fraction[7] | ~xbs_fraction[6])}};
  assign concat_27867 = {literal_27762, and_27851, priority_sel_2b_2way({~(xbs_fraction[3] | xbs_fraction[2] | nor_27838), and_27851}, literal_27794, {literal_27762, ~(xbs_fraction[1] | ~xbs_fraction[0])}, {nor_27839, ~(xbs_fraction[3] | ~xbs_fraction[2])})};
  assign leading_zeroes = and_27842 & and_27855 ? concat_27867 : {literal_27750, ~(~and_27842 | and_27855) ? concat_27862 : concat_27863};
  assign cancel_fraction = leading_zeroes >= 4'hd ? 13'h0000 : {literal_27750, xbs_fraction} << leading_zeroes;
  assign cancel_fraction__1 = cancel_fraction[11:1];
  assign carry_fraction__1 = {xbs_fraction[11:2], xbs_fraction[1] | xbs_fraction[0]};
  assign shifted_fraction = carry_bit ? carry_fraction__1 : cancel_fraction__1;
  assign normal_chunk = shifted_fraction[2:0];
  assign fraction_shift__3 = 3'h4;
  assign half_way_chunk = shifted_fraction[3:2];
  assign do_round_up = normal_chunk > fraction_shift__3 | half_way_chunk == 2'h3;
  assign add_27887 = {literal_27750, shifted_fraction[10:3]} + {literal_27760, do_round_up};
  assign rounding_carry = add_27887[8];
  assign add_27900 = {literal_27750, x_bexp} + 9'h001;
  assign sub_27901 = {4'h0, rounding_carry} - {literal_27750, leading_zeroes};
  assign fraction_is_zero = add_27802 == 10'h000 & ~(shrl_27790[1] | shrl_27790[2]) & ~(shrl_27790[0] | sticky);
  assign wide_exponent_associative_element = {literal_27750, add_27900};
  assign wide_exponent_associative_element__1 = {{5{sub_27901[4]}}, sub_27901};
  assign wide_exponent = wide_exponent_associative_element + wide_exponent_associative_element__1;
  assign wide_exponent__1 = wide_exponent & {10{~fraction_is_zero}};
  assign MAX_EXPONENT = 8'hff;
  assign wide_exponent__2 = wide_exponent__1[8:0] & {9{~wide_exponent__1[9]}};
  assign eq_27915 = x_bexp == MAX_EXPONENT;
  assign eq_27916 = x_fraction == literal_27774;
  assign eq_27917 = y_bexp == MAX_EXPONENT;
  assign eq_27918 = y_fraction == literal_27774;
  assign fraction_shift__2 = 3'h3;
  assign is_operand_inf = eq_27915 & eq_27916 | eq_27917 & eq_27918;
  assign and_reduce_27936 = &wide_exponent__2[7:0];
  assign has_pos_inf = ~(~eq_27915 | ~eq_27916 | x_sign) | ~(~eq_27917 | ~eq_27918 | y_sign);
  assign has_neg_inf = eq_27915 & eq_27916 & x_sign | eq_27917 & eq_27918 & y_sign;
  assign rounded_fraction = {add_27887, normal_chunk};
  assign fraction_shift__1 = rounding_carry ? fraction_shift__3 : fraction_shift__2;
  assign shrl_27949 = rounded_fraction >> fraction_shift__1;
  assign is_result_nan = ~(~eq_27915 | eq_27916) | ~(~eq_27917 | eq_27918) | has_pos_inf & has_neg_inf;
  assign result_sign = priority_sel_1b_2way({add_27802[9], fraction_is_zero}, x_sign & y_sign, ~y_sign, y_sign);
  assign result_fraction = shrl_27949[6:0];
  assign sign_ext_27955 = {7{~(is_operand_inf | wide_exponent__2[8] | and_reduce_27936 | ~((|wide_exponent__2[8:1]) | wide_exponent__2[0]))}};
  assign result_sign__1 = is_operand_inf ? ~has_pos_inf : result_sign;
  assign result_fraction__3 = result_fraction & sign_ext_27955;
  assign FRACTION_HIGH_BIT = 7'h40;
  assign result_sign__2 = ~is_result_nan & result_sign__1;
  assign result_exponent__2 = is_result_nan | is_operand_inf | wide_exponent__2[8] | and_reduce_27936 ? MAX_EXPONENT : wide_exponent__2[7:0];
  assign result_fraction__4 = is_result_nan ? FRACTION_HIGH_BIT : result_fraction__3;
  assign out = {result_sign__2, result_exponent__2, result_fraction__4};
endmodule